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Enhancement of dc bus voltage utilization for a five-level inverter with single dc source and capacitor-fed H-bridge (CHB) units is investigated in this paper. A carrier-based modulation technique is used for boosting the dc bus utilization, which is established by providing detailed mathematical analysis. The five-level inverter used here is realized by cascading a CHB unit to each phase of a three-level neutral point clamped inverter. The increase in dc bus voltage utilization owes to the pole voltage redundancies offered by CHB units. The floating capacitors of H-bridge units are balanced within a quarter fundamental cycle using the switching state redundancies of pole voltage levels. The aforementioned modulation technique allows the inverter to enhance the dc bus utilization from 0.577 $\text{V}_{\text{dc}}$ to 0.63 $\text{V}_{\text{dc}}$ under unity power factor. This enhancement is obtained in the linear modulation range without increasing the dc bus voltage, and thus, the inverter can operate without the presence of low-order harmonics in its phase voltages. The strength of this paper lies in its detailed mathematical analysis for finding out the limiting modulation index and power factor condition in the light of floating capacitor voltage balancing issue. Simulation as well as experimental verification of the modulation scheme is carried out on an induction motor drive under various operating conditions. It is shown that this carrier-based modulation technique is suitable for any single source inverter topology with one CHB unit per phase. [ABSTRACT FROM AUTHOR]

This paper proposes a split-capacitor four-wire current source inverter, which is the dual of the split-capacitor four-wire voltage source inverter. Since the midpoint of the dc link is tied to the neutral point of ac filter capacitors, the common-mode voltage (CMV) is reduced significantly. Consequently, the leakage current issue is effectively addressed. The proposed circuit is cost-effective as no extra switch is added. This paper, first, establishes the equivalent common-mode circuit of the proposed inverter. The impact of the neutral line inductance on CMV is also analyzed. Then, a specific modulation is introduced to balance the dc-link voltages/currents. To achieve good input/output performance, a nonlinear control method is developed based on time-domain models. Finally, all the proposed methods and related theoretical analysis are verified by simulations and experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes a current-fed single-phase inverter without constant intermediate DC link. It eliminates electrolytic capacitor from the DC-link and introduces an intermediate pulsating DC bus. The proposed topology is modular with three full-bridges making it scalable for high-power applications. New pulsating-DC-modulation for back-end pulsating DC-link inverter and secondary modulation (SM) for front-end DC-to-pulsating DC converter is proposed. Soft-switching and device voltage clamping of both primary side and secondary side devices of front-end current-fed full-bridge converter is realized. A rotating partial hybrid pulsewidth modulation has been introduced. One leg of inverter is commutated at a low switching frequency, while the other leg is operated at a high switching frequency for partial period of a line frequency cycle. Thus, switching losses of the back-end inverter are considerably reduced. Rotating mechanism is used to equalize the switching losses of four switches of the inverter. This paper presents detailed operation and analysis of the topology with a proposed modulation scheme. Simulation and experimental results validate the effectiveness and accuracy of the proposed modulation scheme as well as soft-switching and performance of the converter. [ABSTRACT FROM PUBLISHER]

In this paper, a static synchronous compensator (STATCOM) is proposed in which a new modular structure with conventional three-phase voltage source inverters is used to multilevel operation. The inverters are connected to a transformer in an open-end winding configuration and with three independent DC links. In this structure, the inverters will be connected in a cascade configuration. Besides the multilevel operation, the system is also characterized by low required blocking voltages for switch ratings, since the proposed STATCOM can apply the double of the DC capacitor voltage to the transformer windings. The development of the control system for the proposed topology is also presented. The operation of the proposed topology and the performance of the developed control system will be tested through several simulation and experimental tests. [ABSTRACT FROM AUTHOR]

In this paper, a new space vector pulse width modulation method to extend the linear modulation range of a cascaded five level inverter topology with a single dc supply is presented. Using this method, the inverter can be controlled linearly and the peak phase fundamental output voltage of the inverter can be increased from 0.577 to 0.637 V\text{dc} without increasing the dc bus voltage and without exceeding the induction motor voltage rating. This new technique makes use of cascaded inverter pole voltage redundancy and property of the space vector structure for its operation. Using this, the induction motor drive can be operated till the full speed range (0–50 Hz) with the elimination of lower order harmonics in the phase voltage and phase current. The five-level topology presented in this paper is realized by cascading a two-level inverter and two full bridge modules with floating capacitors. The inverter topology and its operation for extending the modulation range is analyzed extensively. Simulation and experimental results for both steady-state and dynamic operating conditions are presented in this paper. [ABSTRACT FROM AUTHOR]

Increasing demands for power supplies have contributed to the population of high-frequency ac (HFAC) power distribution system (PDS), and in order to increase the power capacity, multilevel inverters (MLIs) frequently serving as the high-frequency (HF) source-stage have obtained a prominent development. Existing MLIs commonly use more than one voltage source or a great number of power devices to enlarge the level numbers, and HF modulation (HFM) methods are usually adopted to decrease the total harmonic distortion (THD). All of these have increased the complexity and decreased the efficiency for the conversion from dc to HF ac. In this paper, a nine-level inverter employing only one input source and fewer components is proposed for HFAC PDS. It makes full use of the conversion of series and parallel connections of one voltage source and two capacitors to realize nine output levels, thus lower THD can be obtained without HFM methods. The voltage stress on power devices is relatively relieved, which has broadened its range of applications as well. Moreover, the proposed nine-level inverter is equipped with the inherent self-voltage balancing ability, thus the modulation algorithm gets simplified. The circuit structure, modulation method, capacitor calculation, loss analysis, and performance comparisons are presented in this paper, and all the superior performances of the proposed nine-level inverter are verified by simulation and experimental prototypes with rated output power of 200 W. The accordance of theoretical analysis, simulation, and experimental results confirms the feasibility of proposed nine-level inverter. [ABSTRACT FROM AUTHOR]

Impedance-source networks are an increasingly popular solution in power converter applications, especially in single-stage buck–boost power conversion to avoid additional front-end dc–dc power converters. In the survey papers published, no analytical comparisons of different topologies have been described, which makes it difficult to choose the best option. Thus, the aim of this paper is to present a comprehensive analytical comparison of the impedance-source-based buck–boost inverters in terms of passive component count and semiconductor stress. Based on the waveform of the input current, i.e., with or without a transformer, and with or without inductor coupling, the impedance-source converters are classified. The main criterion in our comprehensive comparison is the energy stored in the passive elements, which is considered both under constant and predefined high frequency current ripple in the inductors and the voltage ripple across the capacitors. Two-level and multilevel solutions are described. The conclusions provide a “one-stop” information source and a selection guide of impedance-source-based buck–boost inverters for different applications. [ABSTRACT FROM PUBLISHER]

Aimed at the problem that the auxiliary commutation circuit (ACC) of auxiliary resonant commutated pole (ARCP) inverters has a high loss in commutation processes, this paper presents a novel modulation strategy with shunt dead time based on a double ARCP (DARCP) inverter. In comparison with the original modulation strategy, this modulation strategy cannot only achieve soft switching for all switches, but also avoid the superposition of resonance current and load current at commutation moments in double ACCs (DACCs) and make the maximum current through DACCs approximately equal to load current in commutation processes. So, the circulating current loss in DACCs and the current stress of auxiliary switches can be effectively reduced. According to the equivalent circuits in different operation modes under the novel modulation strategy, this paper analyzes the operation principle, soft-switching implementation condition, and optimal parameter design procedure of the DARCP inverter. Finally, a 10-kW–16-kHz DARCP inverter prototype with insulated gate bipolar transistor-based switches is built. Experimental results are given to demonstrate the validity and features of the DARCP inverter under the novel modulation strategy. [ABSTRACT FROM AUTHOR]

In this paper, a new hybrid modulation fault-tolerant control of an open-end winding linear vernier permanent-magnet (OEW-LVPM) motor is proposed. By using a floating capacitor inverter, the proposed OEW-LVPM motor drive can continue operation under open-circuit fault condition. The OEW-LVPM motor fed by dual-inverter system consists of two inverters, which are connected to both ends of the motor windings, including a dc power named as main inverter (MI) and a floating capacitor called as capacitor inverter (CI). When one switch is broken in the CI, the CI topology will be restructured to a three-phase four-switch inverter. Then, an improved six-step modulation is investigated in the MI to reduce the switching frequency, while the conventional modulation is applied in the CI. Thus, the MI can provide all the active power, and the CI is only used to supply the reactive power. The proposed fault-tolerant control method is simulated and the experiments with the OEW-LVPM motor drive are also accomplished to verify the feasibility. [ABSTRACT FROM AUTHOR]

Transformerless photovoltaic (PV) grid-connected inverters have become more and more popular in distributed PV power generation systems due to the advantages on high efficiency, low cost, and small size. However, common-mode (CM) current in the transformerless PV inverters can result in serious electromagnetic interference and insecurity, which will further reduce the reliability of the PV inverter systems. In this paper, an improved H5 topology, namely H5-D topology, is proposed, in which a clamping diode is added on the basis of H5 topology to eliminate the CM voltage fluctuation in H5 topology. Further, the PSIM simulation results of the H5-D topology and H5 topology are given and compared, especially, the performance of H5-D topology for CM current suppression is presented and analyzed concretely. Finally, the experimental prototypes of the H5-D topology and H5 topology are built and tested, and the experimental results validate the advantages of the H5-D topology. The proposed H5-D topology provides a new practical topology for distributed PV grid-connected power generation systems. [ABSTRACT FROM AUTHOR]

This paper proposes a control method for a five-level hybrid flying-capacitor (5L-HFC) inverter, of which structure stems from the conventional five-level active neutral-point-clamped (5L-ANPC) topology by dividing the dc-link stage into three series-connected capacitors. In this inverter, the voltage stress on the power switches connected to the dc link is reduced by a half compared with that of the 5L-ANPC topology, thus the lower number of equally voltage-rated power devices can be employed. Also, the power losses in the 5L-HFC inverter are more evenly distributed than in the 5L-ANPC. In order to balance the dc-link capacitor voltages, a third-order harmonic offset injection is applied. When a diode rectifier is used to supply the dc bus voltage, the balancing method is not effective if the modulation index is higher than 0.64. Thus, an auxiliary circuit is needed to support the balancing of the dc-link capacitor voltages. However, the unbalancing problem can be overcome in a full-range operation without the auxiliary circuit if the back-to-back configuration is utilized. Finally, simulation and experiment results have verified the performance of the 5L-HFC inverter with the proposed control method. [ABSTRACT FROM AUTHOR]

This paper investigates the open-circuit faults of switching devices in the three-level T-Type inverter and proposes a new tolerant control method. The three-phase current and variation of the neutral-point voltage are detected to determine the fault switch. A carrier-based pulse width modulation is developed to tolerate switch fault by transiting from three-level to two-level switching. This makes the modulation scheme easier to be implemented compared to space vector modulation. For the neutral-point fault, the fault phase is operated by two-level modulation to produce the same rating voltage. On the other hand, the inverter is able to produce balanced voltage with reduced rating by keeping the phase of half-bridge fault to the neutral-point voltage. The neutral-point voltage is also able to be balanced by using two-level modulation since it does not contribute the neutral-point current. The performance and effectiveness of the proposed tolerant control are verified by a laboratory build. [ABSTRACT FROM AUTHOR]

Owing to low cost, small size, and low weight, transformerless inverters became prominent in single-phase grid connected photovoltaic (PV) systems. Key issues pertaining to these inverters include suppression of common mode (CM) leakage current and improvement of conversion efficiency. Achieving higher efficiency in single-phase grid-connected photovoltaic systems depends on the number of stages involved in feeding power to the grid, predominantly, if the PV array voltage is less than the peak value of the grid voltage. In this paper, an integrated dc–dc converter based grid-connected transformerless PV inverter is proposed which is aimed at maintaining high efficiency, even if the PV array voltage falls below the peak value of grid voltage (efficient operation at an extended input voltage range). A modulation strategy is discussed in order to minimize the flow of CM leakage current. Further, the efficiencies of certain transformerless inverter topologies are analyzed and compared with that of the proposed topology. Detailed simulation studies are carried out in MATLAB/Simulink environment to verify the analysis. Experimental results for a scaled down laboratory prototype are included as a proof-of-concept to validate the claims. [ABSTRACT FROM AUTHOR]

Nowadays, a multilevel converter represents a good idea for commercial and industrial applications, where small size and cost, low maintenance, reliability in a wide range of environments, and good efficiency are required. Furthermore, the multilevel converter can provide control for both maximum power tracking and output power factor reducing the filter weight and volume. The proposed power converter topology, called five-level E-type inverter (5L E-Type Inverter), for grid-connected applications is presented and analyzed in this paper. The performance of the three-phase 5L E-Type Inverter has been theoretically investigated. The thermal models of the power semiconductor have been created taking into account the parameters provided by the manufactures and employing multidimensional lookup tables in the Plexim/PLECS environment. The design and selection of passive components have been described in order to obtain amazing performances in terms of weight, volume, and efficiency and power quality. New control strategy, named concurrent control, for 5L E-Type Inverter has been implemented and validated in the LabVIEW development environment. The peak efficiency of the converter above 98.3% and the total harmonic total harmonic distortion current (THDi) less than 3% have been achieved. [ABSTRACT FROM AUTHOR]

In order to solve the neutral-point voltage unbalancing problem for three-level inverters, this paper proposes a method to balance the neutral-point voltage for three-level inverters with variable modulation wave offset sinusoidal pulse-width modulation (SPWM) control. Based on the mathematical expressions of neutral-point voltage unbalancing, the factors are studied, which affect the fluctuation of neutral-point voltage. Theoretically the mathematical expressions of the neutral-point voltage with the proposed method are derived, and the mathematical relationship between the fluctuation of neutral-point voltage and the adjusting offset of modulation wave is studied. This proposed method realizes controlling the neutral-point voltage balance by dynamically calculating the offset superimposed to the modulation wave based on SPWM (DCOSPWM). This DCOSPWM method is very simple, which has good steady-state performance and is easy for digital implementation. The simulation results verify the correctness of the theoretical analysis in this paper, and the feasibility and effectiveness of this method is verified by the experiments in the experimental platform of neutral point clamped three-level inverters based on digital signal processor (DSP)-complex programmable logic device (CPLD). [ABSTRACT FROM AUTHOR]

This paper is concerned with the use of a three-level inverter for a synchronous reluctance machine (SynRM). The SynRM suffers from a poor power factor due to poor machine saliency. This makes it harder to operate the three-level neutral-point-clamped inverter due to a strict requirement to have the two dc-link capacitor voltages balanced. This paper proposes a new nearest three vector modulation algorithm which can balance the two dc-link capacitors even at poor machine saliency ratio (poor power factor). In this paper, a method of sizing the two dc-link capacitors based on the machine power is also proposed. A comparison between two- and three-level inverters was conducted. The SynRM registered lower $d$-axis current ripple with a three-level inverter, indicating lower core losses in the machine. [ABSTRACT FROM PUBLISHER]

Induction heating technology is leading technical advances in home appliances due to the benefits inherent to the contactless energy transfer including high efficiency, fast heating, safety, cleanness, and accurate control, among others. Recent design trends are focused on developing more versatile cooking appliances for an improved user performance. To achieve such implementations, new multicoil architectures and power converters must be developed. This paper proposes the series-resonant multiinverter as an efficient, versatile, and cost-effective alternative to supply multiinductor systems. One of the main design challenges is the high blocking voltage of power devices, which may compromise the converter performance. This paper proposes an optimized modulation strategy to reduce the maximum device voltage, enabling an optimized converter design with improved reliability and performance. The proposed modulation is analytically studied and tested using a multicoil induction heating converter prototype, proving the feasibility of this proposal. [ABSTRACT FROM PUBLISHER]

This paper proposes a vector control strategy for independent control of two permanent-magnet synchronous motors (PMSMs) using a single four-leg inverter (4LI). An expanded two-arm modulation to obtain a balanced three-phase output voltage is described. This paper also proposes a method to compensate for the fluctuations in the neutral point voltage of two split capacitors in the dc link. The experimental results show that independent speed and position control of two PMSMs can be achieved using a single 4LI with the proposed vector control method. [ABSTRACT FROM AUTHOR]

A multilevel inverter topology for a four-pole induction-motor drive is presented in this paper, which is constructed using the induction-motor stator winding arrangement. A single dc source with a less magnitude when compared with conventional five-level inverter topologies is used in this topology. Therefore, power balancing issues (which are major challenges in conventional multilevel inverters) are minimized. As this configuration uses a single dc source, it provides a path for zero-sequence currents because of the zero-sequence voltages present in the output, which will flow through the motor phase winding and power electronic switches. To minimize these zero-sequence currents, sine–triangle pulsewidth modulation (SPWM) is used, which will shift the lower order harmonics near to switching frequency in the linear modulation region. However, in the case of overmodulation, harmonic voltages will be introduced close to the fundamental frequency. In this regard, a modified SPWM technique is proposed in this paper to operate the drive in the overmodulation region up to the modulation index of 2/\!\surd3. The proposed quad two-level inverter topology is experimentally verified with a laboratory prototype on a four-pole 5-hp induction motor. Experimental results show the effectiveness of the proposed topology in the complete linear modulation region and the overmodulation region. [ABSTRACT FROM PUBLISHER]

Multilevel inverters with dodecagonal (12-sided polygon) voltage space vector structure have advantages, such as complete elimination of fifth and seventh harmonics, reduction in electromagnetic interference, reduction in device voltage ratings, reduction of switching frequency, extension of linear modulation range, etc., making it a viable option for high-power medium-voltage drives. This paper proposes two power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles (for the first time) with minimum number of dc-link power supplies and floating capacitor H-bridges. The first power topology is composed of two hybrid cascaded five-level inverters connected to either side of an open-end winding induction machine. Each inverter consists of a three-level neutral-point-clamped inverter, which is cascaded with an isolated H-bridge making it a five-level inverter. The second topology is for a normal induction motor. Both of these circuit topologies have inherent capacitor balancing for floating H-bridges for all modulation indexes, including transient operations. The proposed topologies do not require any precharging circuitry for startup. A simple pulsewidth modulation timing calculation method for space vector modulation is also presented in this paper. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any offline computation, lookup tables, or angle computation. Experimental results for steady-state operation and transient operation are also presented to validate the proposed concept. [ABSTRACT FROM PUBLISHER]

In this paper, a method is proposed to investigate the dc-link current and voltage ripple calculations in voltage source inverters by considering the reverse recovery of the antiparallel diodes. The impact of the diode reverse recovery transient on the dc-link current and voltage within the switching period is first analyzed. The analysis indicates that the current ripple rms value is affected by the value of inverter switching frequency, diode reverse recovery time, and current. However, the diode reverse recovery shows negligible impact on the dc-link voltage ripple calculation, since the difference between the voltage ripples calculated by the proposed and existing method is less than 1%. To evaluate the estimation accuracy of the dc-link current ripple rms value by the proposed method, the experiments are implemented and the comprehensive analysis is done under different operating conditions, including various power factors, modulation indexes, inverter output currents, and inverter switching frequencies. Experimental results show that the accuracy of dc-link rms current ripple calculation by the proposed method is in the range of $\pm$5% and increased by up to 7% compared with the existing method neglecting the antiparallel diode reverse recovery. [ABSTRACT FROM AUTHOR]

Space vector modulation (SVM) is a widely used method for multilevel inverters. Most of the SVM methods are nearest three vector (N3V) based schemes. Therefore, several researchers have proposed advanced implementation algorithms with reduced complexity for N3V methods. However, topologies like neutral point (NP) clamped inverter (NPCI) require some distinctive methods (called as non-N3V methods) to balance NP voltage for high modulation index and low power factor operations. Currently, the existing non-N3V methods exercise highly complex algorithms for duty ratio calculation and subtriangle identification. This paper presents a new approach, suitable for both N3V and non-N3V methods, with reduced implementation complexity. The proposed algorithm is based on an equivalent two-level space vector diagram and does not require any trigonometry, coordinate transformation, or volt-second balance solution. Unlike other carrier-based methods, it can change the switching sequence as well as the duration of redundant vectors. Moreover, the proposed approach does not require extra steps for implementing hybrid modulation and it can also be extended to multilevel topologies. One N3V, two non-N3V, and hybrid methods are developed using the proposed modulation algorithm, and are compared in detail. Simulation and experimentation on a three-level NPCI verify the validity of the proposed algorithm. [ABSTRACT FROM PUBLISHER]

In this paper, finite-set model-predictive control (FS-MPC) methodologies for a grid-connected three-level neutral-point-clamped converter are investigated. The proposed control strategies produce fixed switching frequency, maintaining all the advantages of predictive control such as fast dynamic response, inclusion of nonlinearities and restrictions, and multivariable control using a single control loop. The first of the proposed FS-MPC strategies is based on a multiobjective cost function, designed to regulate both the inverter currents and the balancing of the dc-link capacitor voltages. The second FS-MPC strategy is derived from the first one, and it is based on a cost function that regulates only the grid current, with the balancing of the capacitor voltages being realized by controlling the duty cycles of the redundant vectors. The proposed control systems are experimentally validated using a 5-kW prototype. The experimental results show a good performance for both strategies, in steady-state and transient response, with a total harmonic distortion lower than \text2\% for the currents supplied to the grid. [ABSTRACT FROM PUBLISHER]

The hybrid modulation strategy using both low-frequency square-wave modulation and high-frequency pulse-width modulation can extend the stable operating region of a cascaded H-bridge converter. However, it does not control accurately dc voltages of converter but balances them by charging or discharging dc capacitors based on the state of system, which could aggravate fluctuation of dc voltages. If cascaded H-bridge converter is used in photovoltaic field, the aggravated fluctuation on dc capacitor voltages will result in further losses in energy harvesting of solar cells. To address this issue, a modified hybrid modulation strategy is presented in this paper. When dc-bus measured voltages are close to their reference voltages, these H-bridges operate in a zero mode. Adding appropriate zero state can prevent grid current charging or discharging the dc capacitors whose voltages have already reached their control goals. Therefore, the proposed technique is capable of suppressing dc voltage fluctuation, and, thus, improving the output power of solar cells. Simulation and experimental results validate the effectiveness and feasibility of the proposed method. [ABSTRACT FROM PUBLISHER]

This paper presents an optimized topology of 3-$\phi$ , multilevel inverter (MLI) configuration for five or higher level operation with reduced switch count. The proposed solution consists of two basic units (BUs) of multilevel converter and a T-structured 3-level inverter (3-LI). Both BUs are equally shared by the three phases maintaining symmetry among the phases. Moreover, for a higher level operation of the proposed MLI, the modifications required are at two BUs only and not at three legs of the inverter. It further helps in reducing the requirement of extra components for higher level operation compared to the conventional solutions. Furthermore, the topology also has the benefits of reduced switching and conduction loss. An algorithm is also devised to generate the switching pulses for the BUs and the 3-LI, using a carrier-based space vector modulation technique. Presented topology is compared with other existing topologies to prove its advantage. All the details regarding the operating modes and pulse width modulation techniques employed for the proposed system are given and supported by the simulation and experimental results. [ABSTRACT FROM AUTHOR]

Adding the auxiliary switches to the conventional H-bridge inverter is an effective way to eliminate the leakage current for transformerless PV systems, such as H5, H6, etc. Inspired by the newly developed embedded-switch H6 topology, a novel embedded-switch inverter (ESI) is proposed in this paper for three-phase transformerless PV systems. First, the operation principle and characteristics of the proposed ESI are analyzed. Second, the common-mode model of the three-phase ESI is established, based on which the main factors that affect the leakage current are discussed. The finding reveals that the switching states with conventional modulation strategy result in high-frequency common-mode voltage, which is the source of leakage current. In order to solve the problem, a new modulation strategy is presented for ESI to eliminate the high-frequency leakage current. Finally, the time-domain simulation and the experimental tests are carried out. The results verify the effectiveness of the proposed solution. [ABSTRACT FROM AUTHOR]

Multilevel current-source inverters have proved to be a high-performance option for industrial applications due to reliability, fault-tolerant capabilities, quasi soft switching, and the use of lower filter capacitor values. One of its major challenges is to balance the internal currents that feed each module. Imbalances could be caused by manufacturing deviations of the reactive components, temperature drift or aging, nonlinear loads, and modulation errors, among others. Using the well-known phase-shift carrier sinusoidal pulse width modulation, a slight change in the amplitude of the carrier signals produces a variation in the average value of the internal currents. In this paper, we introduce a control strategy to balance the current of the inductors and its implementation in a prototype. Simulation and experimental results at different operating conditions show a robust behavior of the control system along with a low distortion in the output voltages and currents of the converter. [ABSTRACT FROM PUBLISHER]

This paper proposes a family of novel flying capacitor transformerless inverters for single-phase photovoltaic (PV) systems. Each of the new topologies proposed is based on a flying capacitor principle and requires only four power switches and/or diodes, one capacitor, and a small filter at the output stage. A simple unipolar sinusoidal pulse width modulation technique is used to modulate the inverter to minimize the switching loss, output current ripple, and the filter requirements. In general, the main advantages of the new inverter topologies are: 1) the negative polarity of the PV is directly connected to the grid, and therefore, no leakage current; 2) reactive power compensation capability; and 3) the output ac voltage peak is equal to the input dc voltage (unlike neutral-point-clamped and derivative topologies, which requires twice the magnitude of the peak ac voltage). A complete description of the operating principle with modulation techniques, design guidelines, and comprehensive comparisons is presented to reveal the properties and limitations of each topology in detail. Finally, experimental results of 1-kVA prototypes are presented to prove the concept and theoretical analysis of the proposed inverter family for practical applications. [ABSTRACT FROM PUBLISHER]

Four-level nested neutral-point clamped (NNPC) inverters experience severe voltage balancing problems under low output-frequency conditions when the conventional four-level space vector modulation (4L-SVM) technique is applied, which limits their wider application. In order to get a complete control of the flying-capacitor voltages, and to alleviate the calculation burden of conventional 4L-SVM, a simplified but effective 4L-SVM technique along with the voltage balance control (VBC) function is proposed in this paper. For low modulation indexes, zero and small vectors are selectively utilized and distributed to force the average charging and discharging time of flying capacitors to be equal to each other during every switching period, so that voltage ripples are greatly reduced to be within an acceptable level under low output-frequency conditions. For high modulation indexes, the simplification of conventional 4L-SVM for NNPC inverters into two-level SVM is proposed to reduce the computation complexity. Principles of the proposed 4L-SVM and VBC are elaborated in detail. The steady-state, transient-state, and VBC performances are investigated and compared with the case where the conventional 4L-SVM is applied. Simulation results of a 5 MVA inverter system and experimental results of a scaled-down 5 kVA inverter system are presented to validate the proposed method. [ABSTRACT FROM PUBLISHER]

Flying capacitor photovoltaic (PV) inverters have been widely discussed in the literature. However, the relevant leakage current issues have not received much attention. In this paper, the modulation techniques for a transformerless three-phase flying capacitor PV inverter are investigated for the leakage current suppression. First, the theoretical analysis of the system common mode model and leakage current is presented. Second, three kinds of conventional carrier-based modulation techniques are evaluated, and results indicate that they fail to effectively suppress the leakage current. Third, a new carrier modulation and logic function is presented. It is able to maintain the constant common mode voltage, and consequently, the leakage current can be significantly reduced. Finally, the experimental tests are conducted on a transformerless three-phase flying capacitor PV inverter to verify the effectiveness of the proposed method. [ABSTRACT FROM PUBLISHER]

Due to a substantial shortage of conventional energy sources, the utilization of renewable energy is gaining attention. Power converters form interfaces to provide power from renewable energy sources to end user systems. Impedance-source inverters (ZSIs) have become a research hotspot and are widely used to overcome the drawbacks of conventional voltage-source inverters and current-source inverters such as two-stage power conversion and less immunity to electromagnetic interference noises. This paper presents various transformer-based ZSIs mainly classified as trans-ZSIs, improved trans-ZSIs, inductor-capacitor-capacitor transformer ZSI, TZSIs, and their comparisons with a new family of ZSIs called Γ-Z-source inverters (ΓZSI). Full operational analysis of an improved ΓZSI with the clamping diode D2 and its benefits over the conventional ΓZSI are also discussed. The improved ΓZSI utilizes a higher modulation index and consequently a lower duty cycle to achieve same gain, thus reducing the switch voltage stress and providing better output quality. Additionally, an extra diode provides voltage clamping to the dc-link voltage to limit voltage overshoots. The comparative evaluations of all the above mentioned ZSIs are presented in the literature and to validate the advantages of the improved ΓZSI, simulations, and experimental comparisons are also performed. [ABSTRACT FROM AUTHOR]

This paper proposes a new nine-level inverter for medium- and high-power applications. The proposed topology comprises of a three-level (3L) active neutral-point-clamped (ANPC) inverter connected in series with a floating capacitor (FC) fed H-bridge. Besides, two additional switches operating at line frequency are appended across the dc link of the 3L ANPC structure. Compared with conventional hybrid cascaded inverters, the primary advantage of this addition is doubling of the resulting root mean square output voltage. This amelioration is achieved while preserving the standard 3L ANPC and H-bridge structures with minimum topological modification. A simple logic-gate-based voltage balancing scheme is developed to regulate the FC voltage. The proposed voltage balancing method is independent of load power factor, inverter modulation index, and can balance the voltage across FC instantaneously. The step-by-step formulation of logical expressions for the generation of gating pulses is deliberated in detail and can be generalized for any $n$-level inverter. Further, simulation results as well as the experimental measurements obtained from the laboratory prototype are presented to validate the effectiveness and practicability of the proposed configuration. Finally, the notable merits of the proposed inverter over the prior art topologies is established through a comprehensive comparative study. [ABSTRACT FROM PUBLISHER]

Three-phase inverters in uninterrupted power supply, electric vehicles, and hybrid electric vehicles use an intermediate dc-link electrolytic capacitor, which has reliability issues and is one prominent cause of inverter failure and limited life. The large volume of an electrolytic capacitor increases the size and cost of the system. Recent research on electrolytic capacitorless inverters using six-pulse modulation technique along with high-frequency power conversion has attempted to address this issue. However, closed-loop operation and control has some issues due to capacitorless dc-link. In this paper, closed-loop operation, design, and implementation of an electrolytic capacitorless inverter is presented. A proof-of-concept 1-kW hardware prototype has been built and tested in a laboratory under different loading conditions. In total, 98% rated efficiency of the inverter is obtained with total harmonic distortion within 2%. Transient results during start-up and load change are smooth, demonstrating safe operation of the inverter. [ABSTRACT FROM AUTHOR]

This paper presents a single-phase ac power supply circuit that based on modified voltage-fed quasi-Z-source inverter topology; it suits to the light or the heavy load and is fit for the resistive, inductive, or capacitive load. The topology, operating principle, voltage gain, control method, and its realization by DSP are described in this paper. The feasibility and rationality of the system is verified by the simulation and experimental results. [ABSTRACT FROM PUBLISHER]

Impedance-source inverters are inverters with voltage-buck–boost capability that cannot be achieved by the traditional inverters. Their boost capability is introduced by shorting their phase legs without causing damages. Impedance-source inverters are therefore less prone to false triggering caused by electromagnetic interference. Present impedance-source inverters are, however, burdened by their low modulation ratio at high input-to-output gain. Such low modulation usually leads to high-voltage stresses across the components and poor spectral performance at the inverter output. To avoid these problems, inverters with coupled transformers have been introduced, but they usually lead to high turns ratio, and hence many winding turns, at high gain. An alternative would then be the asymmetrical \Gamma-source inverters proposed in this paper, whose gain is raised by lowering their turns ratio toward unity. The input current drawn by the proposed inverters is smoother and, hence, more adaptable by the source. Theories and experimental results have been presented in this paper for validating the concepts proposed. [ABSTRACT FROM AUTHOR]

Indirect matrix converter (IMC) is an alternative for ac/ac energy conversion, usually operated with a voltage stepped-down gain of only 0.866. For applications like distribution generation where voltage-boost functionality is required, the traditional style of operating the IMC is therefore not appropriate. Like most power converters, the operation of the IMC can surely be reversed to produce a boosted gain, but so far its relevant control principles have not been discussed. These challenges are now addressed in this paper with distributed generation suggested as a potential application. Simulation and experimental results for validating various performance aspects of the proposed control schemes can be found in a later section of this paper. [ABSTRACT FROM AUTHOR]

Multilevel inverters are receiving more attentions nowadays as one of preferred solutions for medium- and high-power applications. As one of the most popular hybrid multilevel inverter topologies, the five-level active-neutral-point-clamped inverter (5L-ANPC) combines the features of the conventional flying-capacitor type and neutral-point-clamped (NPC) type inverter and was commercially used for industrial applications. In order to further decrease the number of active switches, this paper proposes a seven-switch 5L-ANPC (7S-5L-ANPC) topology, which employs only seven active switches and two discrete diodes. The analysis has shown a lower current rating can be selected for the seventh switch under high power factor condition, which is verified by simulation results. The modulation strategy for 7S-5L-ANPC inverter is discussed. A 1 kVA single-phase experimental prototype is built to verify the validity and flexibility of the proposed topology and modulation method. [ABSTRACT FROM AUTHOR]

For power conversion systems interfaced to four-wire supplies, four-leg converters have become a standard solution. A four-leg converter allows good compensation of zero-sequence harmonics and full utilisation of the dc-link voltage. These are very important features when unbalanced and/or nonlinear loads are connected to the system. This paper proposes a three-dimensional space vector modulation (SVM) algorithm and provides a comprehensive analysis of the algorithm implemented on a three-level, four-leg neutral-point-clamped converter. The algorithm allows a simple definition of the different switching patterns and enables balancing of the dc-link capacitor voltages using the redundancies of the converter states. A resonant controller is selected as the control strategy to validate the proposed SVM algorithm in a 6 kW experimental rig. [ABSTRACT FROM AUTHOR]

Switching sequences of multilevel inverters have to be properly chosen based on the desired control criteria such as dc-link voltage regulation, common mode voltage reduction, and other application dependent criteria. Control of a converter to satisfy a desired criterion is challenging, especially in high voltage level converters. This paper proposes a simple control method for multilevel inverters with high modularity such as flying capacitor multilevel inverters, H-bridge multilevel inverters, and modular multilevel inverters. It is shown that the method considerably simplifies generation of the switching sequences and fulfills the desired criteria with a reasonable computational cost. The proposed method is computationally efficient in the sense that its implementation for high voltage level inverters requires the same effort as required for a multilevel inverter with a low number of cells. Other prominent advantages of the proposed control method, compared to earlier methods, include its applicability for multiphase multilevel converters and converters with asymmetrical structure and/or unevenly distributed dc voltages, independence from the level number and structure of the converter, and not requiring a lookup table. These advantages make the proposed scheme well suited for high cell-number converters, mainly utilized in FACTS, HVDC, and power quality applications. Simulation and experimental results are presented which verify the performance of the proposed method. [ABSTRACT FROM AUTHOR]

The five-phase coupled-inductor inverter is a newly proposed option for three-level five-phase inverter drives. This paper comprehensively analyzes the inverter including the coupled-inductor current, current stress on the dc-link capacitors, and a comparison of these performance aspects using three pulse width modulation (PWM) strategies. Mathematical derivations of the inverter currents and the associated current stress reveal that the current stress is not only influenced by the choice of modulation strategy, as in the neutral-point-clamped topology, but also by the value of coupled inductance; furthermore, the choice of the modulation strategy impacts the core loss of the coupled inductors. Three carrier-based PWM methods are considered: sinusoidal PWM (SPWM), and two methods with the common-mode voltage reduction (referred to as CMVR1 and CMVR2) for the five-phase coupled-inductor inverter. CMVR2 is shown to be the best solution if common-mode voltage reduction is required. The analysis demonstrates that SPWM performs better with respect to current stress and inverter losses, therefore is the preferable modulating strategy for the five-phase coupled-inductor inverter if common-mode voltage reduction is not required. The analysis is verified by simulations and experiments. [ABSTRACT FROM AUTHOR]

In this paper, a control method based on the derivative of power is introduced for single-stage single-phase grid-connected cascaded H-bridge (CHB) photovoltaic inverters. The proposed scheme uses solar arrays derivative of power with respect to current to track maximum power point of each array individually. Using this method along with hybrid modulation technique allows utilization of CHB cells up to their full potential. The control system has a simple structure, and is inherently able to stabilize the system under heavy mismatching conditions where the modulation index goes higher than unity. The effectiveness of the proposed technique is verified by simulation and experimental results. [ABSTRACT FROM AUTHOR]

In this paper, a novel cascaded seven-level inverter topology with a single input source integrating switched-capacitor techniques is presented. Compared with the traditional cascade multilevel inverter, the proposed topology replaces all the separate dc sources with capacitors, leaving only one H-bridge cell with a real dc voltage source and only adds two charging switches. The capacitor charging circuit contains only power switches, so that the capacitor charging time is independent of the load. The capacitor voltage can be controlled at a desired level without complex voltage control algorithm and only use the most common carrier phase-shifted sinusoidal pulse width modulation strategy. The operation principle and the charging–discharging characteristic analysis are discussed in detail. A 1-kW experimental prototype is built and tested to verify the feasibility and effectiveness of the proposed topology. [ABSTRACT FROM AUTHOR]

This paper presents a harmonic elimination technique based on a three-level dodecagonal space vector structure for open-end winding induction motor (IM) drives with a single-dc supply. Advantages of dodecagonal space vector switching and multilevel inverters are achieved with a single-dc supply. A dc supply-fed three-level flying capacitor (FC) inverter feeds active power to one end of the IM winding terminals and H-bridge connected capacitors eliminate fifth- and seventh-order harmonics from the other end. A pulsewidth modulation (PWM) technique is developed to switch the three-level dodecagonal space vectors and simultaneously control the H-bridge capacitors at 0.1445V\text{dc}. The fifth- and seventh-order harmonics are eliminated for the full modulation range of the three-level FC inverter, including the extreme 6-step operation. An increase in the linear modulation range has been achieved, resulting in improved dc bus utilization. Harmonic elimination is achieved by increasing switching frequency of the low-voltage capacitor connected H-bridge inverter; thus, switching frequency for the high-voltage dc supply-fed FC inverter is not increased. Using the proposed scheme, the instantaneous phase voltage never exceeds \frac23V\text{dc} (maximum phase voltage applied for hexagonal space vector structure) for which the machine windings are rated. Additionally, the proposed inverter has also been shown to operate for field oriented control of the open-end winding IM drive. [ABSTRACT FROM AUTHOR]

This paper describes novel single-phase solutions with increased inverter voltage levels derived by means of a nonstandard inverter configuration and impedance source networks. Operation principles based on special modulation techniques are presented. Detailed component design guidelines along with simulation and experimental verification are also provided. Possible application fields are discussed, as well as advantages and disadvantages. Finally, future studies are addressed for the new solutions. [ABSTRACT FROM PUBLISHER]

Yushan et al., and Siwakoti et al., proposed that “the ZSVM4 resulted in the lower current ripples when compared to ZSVM2.” However, some different opinions were presented in this paper. With the space vector modulations (SVMs) strategy, the ZSVM4 results in the lower current ripples when compared to ZSVM2 in parts angle intervals. While in other intervals, the conclusion will be opposite. The maximum current ripple of ZSVM2 is lower than that of ZSVM4. Both simulations and experimental results have verified these theoretical findings. [ABSTRACT FROM PUBLISHER]

Multilevel converters have become an interesting alternative for medium- and high-voltage drives over the last decade. Among the existing alternatives, multicell structures offer advantages due to their modularity and scalability. This paper presents experimental results of a recently introduced multilevel topology. The converter is based on the mixture of the two most popular multicell topologies, namely, flying capacitor and cascaded multicell inverter. The new cell provides a high number of output levels, a low number of components, high modularity, and low losses. The results presented in this paper confirm that this new medium-voltage inverter topology is able to reach high-quality output voltages, allowing further advances in modulation techniques and other issues. [ABSTRACT FROM AUTHOR]

In this paper, two modulation strategies called Mod-1 and Mod-2 are compared for a three-level diode neutral-point-clamped (NPC) inverter synchronous reluctance machine (SynRM) drive. These modulation strategies do not operate at a fixed switching frequency. A new modulation strategy which operates at a fixed switching frequency is proposed called Mod-3. The SynRM suffers from a poor power factor which makes it harder to archive capacitor voltage balancing for a three-level NPC inverter. These modulation strategies are of the nearest three vector (NTV) family. Mod-1 and Mod-3 choose certain vector states to achieve capacitor voltage balancing, whereas Mod-2 strategy makes use of the inverter vector state’s dwell time. The parameters of interest are the torque ripple, the neutral point (NP) voltage ripple, the inverter efficiency, and the $d$-axis current ripple. Though lower torque ripple and better power quality are registered on Mod-2 strategy. Mod-1 strategy has 14% improvement in inverter efficiency at lower modulation index ($m_i = 0.4$). Mod-2 strategy has 11% more NP voltage ripple at a modulation index of 0.4. One of the disadvantages of Mod-1 strategy is the varying switching frequency. Mod-3 scheme produced higher inverter efficiency, better balancing of the capacitor voltages, and guaranteed fixed inverter switching frequency. The disadvantage with Mod-3 strategy is that it generated higher torque ripple, $d$-axis current ripple, and current total harmonic distortion when compared to Mod-1 and Mod-2 at the same load conditions. [ABSTRACT FROM AUTHOR]

Eliminating the leakage current is one of the most important issues for transformerless three-phase photovoltaic (PV) systems. In this paper, the leakage current elimination of a three-phase four-leg PV inverter is investigated. With the common-mode loop model established, the generation mechanism of the leakage current is clearly identified. Different typical carrier-based modulation methods and their corresponding common-mode voltages are discussed. A new modulation strategy with Boolean logic function is proposed to achieve the constant common-mode voltage for the leakage current reduction. Finally, the different modulation methods are implemented and tested on the TMS320F28335 DSP +XC3S400 FPGA digital control platform. The experimental results verify the effectiveness of the proposed solution. [ABSTRACT FROM PUBLISHER]

This paper proposes a new topology for an enhanced-boost Z-source inverter (ZSI) with combined two Z-impedance networks. By two Z-impedance networks and low shoot-through duty cycle, the proposed inverter produces high output voltage gain. In traditional ZSIs for high boosting voltage, a low modulation index is required; hence, under these conditions, the output voltage will have low quality with high total harmonic distortion. Compared with the conventional high-boost ZSI topologies, the proposed inverter uses shorter shoot-through duration and a larger modulation index to improve the output waveform quality. Comparison between the proposed topology and previously proposed schemes, in terms of inductor numbers, voltage and current stresses on elements, sizes of inductors and capacitors, efficiency, and switching device product (SDP) factors of diodes, is made, and the results verify the priority of the proposed topology. The operating principle of the proposed topology is analyzed in detail. Both simulation and experimental results verify the high performance of the proposed inverter. [ABSTRACT FROM PUBLISHER]

Featuring modularity and high efficiency, a modular multilevel converter (MMC) has become a promising topology in high-voltage direct-current transmission systems. However, its distributed capacitors lead to a more complicated startup process than that of a two-level converter. To fully understand this issue, the charging loops of an MMC rectifier and an MMC inverter during an uncontrolled precharge period are analyzed in this paper, with special focus on the necessity of additional capacitor charging schemes. Moreover, a small-signal model of a capacitor charging loop is first derived according to the internal dynamics of the MMC inverter. Based on this model, a novel startup strategy incorporating an averaging capacitor voltage loop and a feedforward control is proposed, which is capable of an enhanced dynamic response and system stability without sacrificing voltage control precision. The design considerations of the control strategy are also given in detail. Simulation results from a back-to-back MMC system supplying passive loads and experimental results from a scaled-down MMC prototype are provided to support the theoretical analysis and the proposed control scheme. [ABSTRACT FROM PUBLISHER]