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This paper introduces a three-phase grid-connected inverter for commercial-scale photovoltaic systems. The circuit topology combines an ac-inductor-less active bridge with a parallel-connected pulsewidth modulation inverter acting as an instantaneous reactive power compensator. The active bridge, called a 120° conduction inverter, operates at a switching frequency equal to the grid frequency and outputs a 120° rectangular current, while the compensator eliminates the harmonic currents included in the rectangular current. The main advantage of this strategy is the reduction in size of the required ac inductor by a factor of 4, as well as the reduction of power losses in the switching devices. The theoretical analysis clearly shows that the compensator can synthesize a sinusoidal output current by controlling only instantaneous reactive power, thus eliminating the need for electrolytic capacitors. A 5-kW experimental setup validates the operating principle and the control method of the proposed inverter and exhibits an inverter efficiency as high as 99.2% with Si superjunction mosfets. [ABSTRACT FROM AUTHOR]

Paralleled inverters are not only a suitable approach to increase the power capacity, but also have the capability of common mode voltage (CMV) reduction, or even elimination. The original zero CMV modulation scheme for paralleled inverters suffers from the current jump problem in phase-leg currents. This current jump phenomenon amplifies the peak values of differential-mode circulating current (DMCC) and zero-sequence circulating current (ZSCC), which is adverse for the design of coupled inductor and common-mode inductor. This paper introduces the modified modulation scheme, which can keep volt-seconds balance in whole fundamental period and mitigate the current jump in phase-leg currents. In addition, the reduction effect of the DMCC and ZSCC can be achieved. To verify the analysis, both the simulation and experimental results are presented, which validates the proposed methods and show that they are beneficial for DMCC and ZSCC reduction. [ABSTRACT FROM AUTHOR]

In this paper, two structures are proposed for the switched-inductor quasi-Z-source inverter. In the proposed structures to extend the voltage gain of inverter, two new switched-inductor structures are used. In the proposed structures, voltage across the capacitors in the Z-source network and in the switched-inductor is symmetric and small. The other advantage of proposed inverters is known as achieving higher voltage gain per smaller duty cycle ratio (of shoot-through). Compared with a conventional continuous input current switched-inductor quasi-Z-source inverter at the same gain voltage, there is less of a ripple of input current in the proposed inverters. In this paper, at first the both the conventional and the proposed switched-inductor Z-source inventers are thoroughly investigated to find out their governing relations. Then, the proposed Z-source inverters are compared with the conventional ones by simulating them to assess their performance efficiency. Next, applying the simple boost pulse width modulation the simulation is carried out with PSCAD/EMTDC software. After that, to evaluate the obtained results, the prototypes of the proposed inverters with 48 Vdc input voltage are used. [ABSTRACT FROM PUBLISHER]

A novel hybrid pulse width modulation (PWM) technique is proposed in this paper for two parallel interleaved, two-level, three-phase voltage source inverters (VSIs). The two parallel interleaved VSIs are analyzed as a three-level (3L) inverter. A 3L inverter provides minimum line current ripple when nearest three voltage vectors are applied. In this paper, a novel carrier-based PWM technique is developed that ensures the application of nearest voltage vectors, keeping average circulating current to zero over a switching period. For carrier-based implementation of the proposed PWM, generalized common-mode (CM) offsets are derived in terms of maximum and minimum values of reference signals. Each 3L space-vector sector is divided into seven subsectors. For each subsector, a CM offset is calculated, addition of which to reference signals ensures the minimum line current ripple and zero average circulating current. Simulation and experimental results are provided to validate the proposed technique. [ABSTRACT FROM PUBLISHER]

The Z-source inverter (ZSI) employs an LC impedance network between the main inverter bridge and the power source. The unique feature of the ZSI is that it can operate either in buck or boost mode with a wide range of obtainable output voltages from a given input voltage. This topology also exhibits better electromagnetic-interference noise immunity when compared to a traditional voltage-source inverter (VSI). However, the LC impedance network of ZSI significantly increases the size and cost of the power converter and can make it unsuitable for low-power applications. This paper proposes a novel topology called switched boost inverter (SBI) which exhibits similar advantages of ZSI with lower number of passive components and more active components compared to ZSI. The steady-state and small-signal analyses of SBI, along with its pulsewidth modulation (PWM) control strategies, have been discussed in this paper. This paper also presents a comparison of SBI and ZSI with the same input and output parameters. The theoretical analysis given in this paper has been validated using a laboratory prototype of SBI, and the experimental results are presented for verification. The experimental harmonic spectrum of the inverter's output voltage with the proposed PWM technique is also plotted and compared with that of a traditional VSI. All the experimental results show good correlation between theory and experiments. [ABSTRACT FROM PUBLISHER]

In several electrical dc–ac power conversions, the ac output voltage is higher than the input voltage. If a voltage-source inverter (VSI) is used, then an additional dc–dc boosting stage is required to overcome the step-down VSI limitations. Recently, several impedance source converters are gaining higher attentions [1], [2], as they are able to provide buck-boost capability in a single conversion stage. This paper proposes the merging of the boost stage and the VSI stage in a single stage dc–ac power conversion, denoted as split-source inverter (SSI). The proposed topology requires the same number of active switches of the VSI, three additional diodes, and the same eight states of a conventional space-vector modulation. It also shows some merits compared to Z-source inverters, especially in terms of reduced switch voltage stress for voltage gains higher than 1.15. This paper presents the analysis of the SSI and compares different modulation schemes. Moreover, it presents a modified modulation scheme to eliminate the low frequency ripple in the input current and the voltage across the inverter bridge. The proposed analysis has been verified by simulation and experimental results on a 2.0-kW prototype. [ABSTRACT FROM PUBLISHER]

This paper proposes a new single-phase single-stage switched-boost inverter with four switches. Like the quasi-Z-source inverter and quasi-switched boost inverter (qSBI), the proposed inverter has the main features as continuous input current, buck/boost voltage with single-stage conversion, and shoot-through immunity. Compared to the qSBI, the proposed inverter uses one more capacitor and one less switch. This paper presents the operating principles, pulse-width modulation control strategy, parameter design guidelines, and simulation results for the proposed inverter. To verify the performance of the proposed inverter, an 800-W prototype was built with an 110 V/50 Hz output voltage in stand-alone and grid-connected modes. The simulation and experimental results matched those of the theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper introduces series work of common-mode (CM) voltage reduction for the paralleled inverters. The paralleled inverters’ phase-legs are connected through coupling inductors and the combined three-phase currents are provided to the load. Interleaving is an approach to reduce the CM voltage for the paralleled inverters but it cannot eliminate CM voltage. A novel pulse-width-modulation (PWM) method for paralleled inverters which can theoretically achieve zero CM voltage is developed. Considering the basic voltage vectors in each inverter, novel paralleled voltage vectors which have zero CM voltage are proposed to combine the reference voltage vector. The action time's distribution and voltage vectors’ sending sequence for each inverter are also introduced. The proposed PWM method can make sure the voltage of the two inverters are balanced in each switching cycle and limits the circulating current through small coupling inductors. Similar to interleaving space vector PWM, the proposed zero CM PWM also has the ability to reduce the output current ripple and electromagnetic interference (EMI). Simulation and experimental results are provided to show the advantage of paralleled inverters in CM voltage reduction and validate the proposed method has good performance to reduce CM current and CM EMI noise. [ABSTRACT FROM PUBLISHER]

A dual-buck inverter (DBI) possesses no shoot-through worries and can boost efficiency by using power mosfet s. The main drawback of a DBI is the use of more inductors than in a traditional full-bridge inverter. This greater number of inductors decreases the power density and increases system cost. In this paper, a modified cascaded full-bridge DBI is proposed. It retains all the advantages of the conventional cascaded full-bridge DBI, possesses no shoot-through issues, and can be operated with no pulse-width-modulation dead-times. It can be implemented with power mosfet without reverse recovery issues of a body diode to boost efficiency. The cascaded modules in the proposed inverter share current limiting inductors. Therefore, the number of inductors and inductor footprints, the complexity of the circuit layout, required inductance, and magnetic volume can all be decreased. To show the advantages of the proposed inverter, detailed theoretical analysis and experimental results are provided. [ABSTRACT FROM PUBLISHER]

This paper introduces a combination of two proposed efficiency improvement techniques for a microinverter with current mode control zero-voltage switching output stages. The first technique is dynamic dead-time optimization wherein pulse width modulation dead times are dynamically adjusted as a function of load current. The second method is advanced phase skipping control which maximizes inverter efficiency by controlling power on individual phases depending on the available input power from the photovoltaic source. Neither of the techniques requires any additional circuit components and both can be easily implemented in digital controller firmware. The two techniques were designed and implemented in a 400-W three-phase microinverter prototype. The experimental results validate the theoretical analysis of these techniques and demonstrate that a significant efficiency improvement can be achieved by combining the two proposed control techniques. [ABSTRACT FROM AUTHOR]

A new single-phase \uppi-\texttype 5-level inverter using 3-terminal switch-network (3TSN) is proposed in this paper. The topology is considered as a variant of T-type 3-level structure or dual-buck inverter with coupled inductors. This new inverter is suitable for multilevel power inversion with low dc-bus voltage. The merit of the proposed topology is to apply only four active power switches to achieve 5-level operation. Other benefits include double frequency operation of output inductor and equal division of the current that flows through power switches and filter inductor. Hence, it leads to high efficiency and low harmonics. These characteristics allow improvement of losses distribution and volume reduction of output filter inductor. The operation scenario with sinusoidal pulsewidth modulation (SPWM) is described in details. Meanwhile, the magnetic analysis and design are studied and discussed. Finally, a prototype is built to verify the theoretical analysis and demonstrate the benefits of the proposed topology. [ABSTRACT FROM AUTHOR]

This paper focuses on the common dc-link voltage between a three-phase diode rectifier and a modular multilevel cascade inverter based on double-star chopper cells (MMCI-DSCC) for a medium-voltage motor drive. This motor drive can be operated even when no capacitor exists on the dc link. However, a nonnegligible, but predictable, amount of switching-ripple voltage occurs on the dc link. This paper achieves modeling and analysis of the switching-ripple voltage, thus making it possible to design a small-sized dc passive filter consisting of series connection of a film capacitor and a damping resistor. A 400-V, 15-kW down scaled system is used to confirm the effectiveness of the analysis and the dc filter. Experimental results show that the switching-ripple voltage can be attenuated satisfactorily by the dc filter, and that the power loss dissipated in the damping resistor is negligible, compared to the rated power of 15 kW. [ABSTRACT FROM AUTHOR]

Pulse-width-modulated (PWM) converters have been widely applied for power processing, and they are typically the stems of other types of converters, such as quasi-resonant, Z-source, and switched-inductor hybrid converters. Development of PWM converters has been spanning over a century, starting from the buck converter. The well-known PWM converters include buck, boost, buck–boost, Ćuk, single ended primary inductive converter (SEPIC), zeta, Z-source, quasi-Z source, etc. Many attempts have been proposed to develop these converters based mostly on canonical cell concepts and by introducing extra LC filters to the cells. This paper presents an enhancement to the layer and graft schemes by introducing the ideas of dc voltage/current offsetting, capacitor/inductor component splitting, diode grafting, and inverse operation of PWM converters. The PWM converters, which can be operated in continuous conduction mode (CCM) or discontinuous conduction mode (DCM), therefore can be synthesized systematically according to decoded transfer gains. Decoding and synthesizing PWM converters uniquely bridge transfer gains to converter topologies and provide readers a comprehensive understanding of PWM-converter evolution from the original converter, the buck converter. Additionally, in this paper, the Ćuk, SEPIC, and zeta converters all with the same transfer gain of $D/(1 - D)$ are proved to be equivalent to the buck–boost converter with an extra LC filter. For further illustrating the proposed approaches, various types of Z-source converters, switched-capacitor/switched-inductor hybrid converters, and a single-stage interleaved converter are reviewed, and new PWM converters are developed. [ABSTRACT FROM AUTHOR]

A zero-voltage switching (ZVS) grid-connected full-bridge inverter and its modulation schemes are investigated. A novel sinusoidal pulse width modulation scheme for the ZVS full-bridge inverter (ZVS SPWM) is proposed in this paper. The ZVS SPWM is evolved from the double-frequency SPWM by adding gate drive to the auxiliary switch. The ZVS condition is analyzed and the circulation loss of the resonant branch is optimized by adjusting the energy storage in the resonant inductor. The reverse recovery of the body-diode of MOSFET is relieved and ZVS is realized for both main and auxiliary switches. The filter inductors are significantly reduced with higher switching frequency. The design guideline of resonant parameters and the implementation of ZVS SPWM in DSP controller are introduced. The ZVS SPWM scheme is verified on a 3-kW inverter prototype. According to the experimental result, peak efficiency as 98.8% is achieved. [ABSTRACT FROM AUTHOR]

Carrier-based pulsewidth-modulation (CBPWM) techniques are popular due to their simplicity, and have been widely researched for various three-phase inverter configurations. In this paper, two CBPWM techniques are proposed to reduce the common-mode (CM) voltage generated by the five-phase inverter. The five-phase inverters have more flexibility in reducing the CM voltage than their three-phase counterparts because they have more phase legs, hence finer control over the star-point voltage of the load. Two methods are proposed for the conventional two-level five-phase inverter to reduce the CM voltage; one utilizing adjacent modulating waveforms and the other utilizing nonadjacent modulating waveforms. The coupled inductor inverter (CII) uses coupled inductors to generate multilevel outputs. As the volt-second balance must be maintained across each coupled inductor, direct application of the proposed methods on the CII inverter will result in overcurrents in the coupled inductors. Hence, the proposed methods are further improved to ensure the volt-second integral over each switching period is zero. Moreover, the two proposed methods are designed to reduce switching events and prevent unexpected states occurring during the switching transitions. The performance and the switching strategy of both methods are verified by both simulations and experiments on a prototype of five-phase CII. [ABSTRACT FROM AUTHOR]

In this paper, a generalized switching modification method is proposed to reduce the root-mean-square (rms) current flowing into a dc-link capacitor in a dc–dc–ac structure consisting of a boost converter and a three-phase inverter. To analyze the current flowing into the capacitor, we analyze the currents at the respective converter and inverter sides. Based on this analysis, we derive an analytical method to find the modification time between the converter and inverter pulsewidth modulation (PWM) carriers through a Fourier series and approximation to facilitate real-time implementation. Real-time implementation of the modification time calculated by the derived method is described. To verify the validity of the proposed method, experimental results are presented based on a 1-kVA dc–dc–ac prototype. The proposed method has a better capacitor rms current reduction performance than the conventional method in various inverter power factors and PWM strategies. Especially, it has an excellent performance in mid-power factor level (0.95–0.1). [ABSTRACT FROM AUTHOR]

This paper proposed a novel family of pulsewidth modulation (PWM) strategies for single-phase quasi-switched boost inverter (qSBI). By combining shoot-through (ST) mode in the inverter's switches and the turning-on state of an additional switch, the qSBI produced a high voltage gain without adding any passive components. Compared to the conventional PWM strategy for the same input and output voltage gain, the introduced PWM strategies for qSBI could reduce voltage stress across semiconductors and capacitor with the following additional merits: having smaller high-frequency inductor current and capacitor voltage ripples, using high modulation index with low ST duty cycle, and having higher efficiency. Circuit analysis, operating theories, and simulation results of the single-phase qSBI with the introduced PWM5 strategy are shown. A 500-W laboratory prototype was constructed and the effectiveness of the introduced PWM strategy was validated. The qSBI with the proposed PWM strategies is suitable for applications where the required voltage gain lies between 2 and 3. [ABSTRACT FROM AUTHOR]

A division–summation (D-\mathbf\Sigma) digital control for three-phase inverters to achieve active and reactive power injection has been presented. It can overcome the limitation of abc to dq frame transformation. However, the D-\mathbf\Sigma control requires four sets of control laws to cover four quadrant operations, namely, grid connection (power factor (PF) 1 $\sim\pm$0.866), rectification with PF correction, PF leading (0 \sim$ 0.866), and PF lagging (0 \sim$ −0.866). Moreover, the switching sequences for the four modes are also different from each other, increasing complexity of firmware programming. In this paper, improvement of the control law derivation and region selection for the (D), which can obtain the control law directly. Measured results from a 10-kVA 3 $\phi$ bidirectional inverter have been presented to confirm the improvement. [ABSTRACT FROM PUBLISHER]

This paper proposes the pulsewidth modulation (PWM) strategy of Z-source inverters (ZSIs) with minimum inductor current ripple. In existing PWM strategy with single-phase shoot-through, the shoot-through time interval is divided into six equal parts, therefore the three phase legs bear the equal shoot-through time interval. In this manner, the allotment and arrangement of the shoot-through state is easy to realize, but the inductor current ripple is not optimized. This causes to use relatively large inductors. In the proposed PWM strategy, the shoot-through time intervals of three phase legs are calculated and rearranged according to the active state and zero state time intervals to achieve the minimum current ripple across the Z-source inductor, while maintaining the same total shoot-through time interval. The principle of the proposed PWM strategy is analyzed in detail, and the comparison of current ripple under the traditional and proposed PWM strategy is given. Simulation and experimental results on the series ZSI are shown to verify the analysis. [ABSTRACT FROM PUBLISHER]

In this paper, a three-level quasi-switched boost T-type inverter (3L qSBT2I) is proposed. A new pulse-width modulated (PWM) control method is presented to reduce the inductor current ripple of the qSBT2 I. In the introduced PWM technique, the shoot-through duty cycle is maintained constant to keep the modulation index as high as possible. Then, the only control parameters of the qSBT2I are the duty cycles of the two additional switches. By controlling the duty cycles of the two additional switches, the voltage gain of the proposed qSBT2 I can be improved to a value larger than that of the conventional 3L impedance source inverters. The steady-state analysis, operating principles, and comparisons with the impedance source-based 3L inverters are presented. A 1-kW prototype is constructed to verify the operating principle of the 3L qSBT2I. An indirect dc-link voltage regulator and a capacitor voltage-balance controller are applied to the proposed qSBT2I. Simulation and experimental results are presented. [ABSTRACT FROM AUTHOR]

This paper investigates a multilevel inverter composed of series/parallel-connected H-bridges. The presented structure can be used for applications in which the use of semiconductor switches with low-voltage and low-current ratings is intended. A comprehensive system model, an overall control strategy to adjust the output voltage with constant magnitude and frequency, and a level-shifted PWM (LS-PWM) strategy based on a voltage vectors unidimensional analysis and a plane analysis are presented. The LS-PWM is capable of mitigating the low-frequency circulating current, thus generating multilevel voltage signals with low harmonic distortion, maximum number of levels, and low dv/dt. In addition, considering a wide range of values of voltages and currents and various power levels, the total converter losses are reduced compared with the conventional multilevel converters. Two multilevel conventional inverters with the same number of semiconductor switches are used for comparison. Simulation and experimental results demonstrate the feasibility of the studied converter. [ABSTRACT FROM AUTHOR]

In this paper, dual-buck structured single-stage buck–boost inverters that use power MOSFETs to achieve high efficiency are presented. The proposed inverters require fewer switches, and half of the switches have reduced current stresses. They have no shoot-through problem; therefore, high system reliability can be obtained. The dead-time in PWM signals can be minimized or eliminated, which improving the quality of the output ac voltages and increasing the efficiency. In the proposed inverters, MOSFETs can be used without reverse-recovery issues of their body diodes to boost the efficiency and increase the switching frequency. To further improve the efficiency and stability of the proposed single-phase inverter, PWM strategies combining high- and low-frequency modulation are presented. A hardware prototype of the single-phase inverter was built and tested using resistive, inductive, and nonlinear loads. Experimental results for a 300-W prototype inverter show a 97.4% peak efficiency with a 25 kHz switching frequency. [ABSTRACT FROM AUTHOR]

In this paper, a novel single-phase five-level inverter is proposed using coupled inductors. This inverter can output five-level voltage with only one dc source. No split of the dc voltage capacitor is needed, totally avoiding the voltage balancing problem in conventional multilevel inverters. The level of the output voltage is only half of the dc-link voltage in all conditions, leading to much reduced dv/dt . This inverter is based on the widely used three-arm power module and the voltage stresses on all the power switches are the same, making it very easy to construct. Operation mechanism of this inverter is analyzed and the possible switching patterns are investigated. Based on these analyses, a novel optimized modulation scheme is presented. With this modulation method, no dc components exist in the inductor currents, which is very helpful for minimization of the inductors. Simulation and experimental results show the validity of the proposed inverter together with the optimized modulation scheme. [ABSTRACT FROM AUTHOR]

This paper presents an alternative to the traditional dc-dc converter interfacing the battery with the inverter dc bus in plug-in hybrid electric vehicle (HEV) traction drives. The boost converter used in commercial HEVs meets with obstacles when it comes to upgrading the power rating and achieving high efficiency while downsizing the converter. A four-level flying-capacitor dc-dc converter is explored that can overcome these drawbacks by dramatically reducing the inductance requirement. A special case of the four-level converter, the 3X dc-dc converter, operates at three discrete output/input voltage ratios, thus further reducing the inductance requirement to a minimal value (almost zero). When further compared to its switched-capacitor dc-dc converter counterparts, the 3X dc-dc converter can be operated at variable output/input voltage ratios without sacrificing efficiency, and it lowers the capacitance requirement by utilizing the parasitic inductance. The operating principle, current ripple analysis, the transient control to limit the inrush current, and power loss analysis are introduced. Experimental results of a 55-kW prototype are provided to demonstrate the principle and analysis of this topology. [ABSTRACT FROM AUTHOR]

A family of isolated buck–boost dc/dc converter for wide input-voltage range is proposed in this paper, and the full-bridge (FB) boost converter, being one of the typical topologies, is analyzed. Due to the existence of the resonant inductor (including the leakage inductor), the FB-boost converter can only adopt the two-edge-modulation (TEM) scheme with the FB cell being leading-edge modulated and the boost cell being trailing-edge modulated to minimize the inductor current ripple over the input-voltage range, and a phase-shift-control-scheme-based TEM with the use of the market available controller IC such as UC3895 is proposed, which realizes phase-shifted control for the FB cell to achieve zero-voltage switching. In order to improve the reliability and efficiency of the FB-boost converter, a three-mode dual-frequency control scheme is proposed, in which the FB-boost converter operates in boost, FB-boost and FB modes in low, medium and high input voltage regions, respectively, and for which the expression of the inductor current ripple is derived in this paper. As the input voltage in the FB-boost mode is close to the output voltage, the inductor current ripple in this mode is much smaller than that in the other modes, and the switching frequency of the boost cell in this mode can be lowered to one-(2N+1)th of the preset switching frequency to reduce the switching loss, and hence, to improve the efficiency. A 250–500 V input, 360 V output, and 6 kW rated power prototype is fabricated to verify the effectiveness of the design and control method. The average efficiency over the input-voltage range is 96.5%, and the highest efficiency attained is 97.2%. [ABSTRACT FROM AUTHOR]

This paper proposes a single-phase, single-stage buck–boost inverter for photovoltaic (PV) systems. The presented topology has one common terminal in input and output ports which eliminates common mode leakage current problem in the grid-connected PV applications. Although it uses four switches, its operation is bimodal and only two switches receive high-frequency pulse width modulation signals in each mode. Its principle of operation is described in detail with the help of equivalent circuits. Its dynamic model is presented, based on which a bimodal controller is designed. Experimental results, in stand-alone and grid-connected mode, obtained with a 300-W laboratory prototype are presented to validate its performance. [ABSTRACT FROM AUTHOR]

A nonlinear pulse width modulation-controlled single-phase boost mode photovoltaic grid-connected inverter with limited storage inductance current is proposed in this paper. The circuit topology, control strategy, steady-state principle characteristic, and design criterion for the key circuit parameters of this kind of inverter are investigated in depth, and important conclusions are obtained. The inverter's regenerating energy duty ratio 1–D which decreases with the decline of the grid-connected voltage is real time adapted by sampling and feeding back the inverting bridge modulation current, and the average value of the modulation current in each switching cycle tracks the reference sinusoidal signal to get high-quality grid-connected current. The active control of the energy storage inductance current and the balance of the voltage step-up ratio are realized by adding a bypass switch connected in parallel with the energy storage inductance and using two kinds of switching pattern namely boost pattern and freewheeling pattern. The theoretical analysis and experimental results of the 1 kVA 110 VDC/220 V50 Hz photovoltaic grid-connected inverter prototype show that it has the advantages such as single-stage boost conversion, high conversion efficiency, high quality of grid-connected current waveform, low value of energy storage inductance, simple control, etc. [ABSTRACT FROM AUTHOR]

This paper identifies the characteristics of a current source inverter operating in discontinuous conduction mode, and proposes a new multiobjective pulse-width modulation (PWM) method to mitigate voltage boosting and harmonic distortion effects. The method takes into account load impedance effects. Controls are also developed to enable transition between the multiobjective PWM method and conventional PWM as the current source inverter operates in discontinuous and continuous modes of operation. The concept is verified experimentally on a 3 kW test bed. [ABSTRACT FROM AUTHOR]

A single-phase inverting buck–boost ac–ac converter is proposed in this paper. The proposed converter has no shoot-through and dead-time problems and, like conventional dc–dc converters, it can be operated with simple pulse width modulation (PWM) control. It offers high frequency and high efficiency operation because high speed mosfet can be used as switching device without the reverse recovery issues and losses of its body diode. The proposed converter features quasi-continuous input and output currents, high input power factor, low total harmonic distortion of input and output currents, and high efficiency. A 460 W laboratory prototype was constructed and tested with interleaved and complementary PWM controls using a resistive and inductive load. Detailed experimental results are provided to show the novelty of the proposed converter. Experimental results confirmed that the proposed converter can obtain 93.8% efficiency at 60 kHz switching frequency. [ABSTRACT FROM PUBLISHER]

In high current applications, paralleling three-phase voltage sourced inverters represents a modular solution for improving the system power conversion quality. Single-phase output reactors are often inserted between the output terminals of the two inverters that supply the same phase output. One function of these inductors is to limit circulating currents between the two inverters. These currents are produced by common-mode voltage differences between the three-phase output terminals of the two inverters. Since standard interleaved pulse width modulation (PWM) techniques naturally produce high-frequency common-mode voltage differences between parallel connected inverters, this paper describes a modified discontinuous PWM scheme that eliminates these voltage differences. As a result, a three-phase parallel inverter system can be operated using a single three-limb coupled inductor, significantly improving the system power conversion density as a result. An experimental 3 kW prototype system is used to compare the operation of the resultant inverter against one using separate single-phase coupled inductors. [ABSTRACT FROM PUBLISHER]

In this paper, a passive lossless snubber circuit for pulse width modulation (PWM) inverters is proposed to achieve soft-switching purpose without extra switch or additional control circuitry. This passive lossless soft-switching snubber employs an inductor/capacitor snubber structure for each switching device in an inverter to achieve passive zero-current turn ON and zero-voltage turn OFF. Furthermore, inductors coupled closely on a single core are used to losslessly recover snubber energy to the input in the proposed snubber. In addition, freewheeling of output phase current of inverters can be realized via energy storage components of the snubber during the dead time to reduce the effect of dead time. The distortion ratio of the output phase current in low output frequency is also reduced. All components in the snubber circuit are passive, and thus have a better price/performance ratio than their active counterparts. The proposed snubber has been incorporated into a 14-kW PWM inverter. Experimental results are given to demonstrate the validity and features of the snubber. [ABSTRACT FROM PUBLISHER]

A five-/nine-level twelve-switch inverter is described for three-phase high-speed electric machines having a low per-unit leakage reactance. By reducing the voltage blocking requirement of the semiconductors, the neutral-point-clamped (NPC) variant of the coupled inductor (CI) inverter topology (NPC-CI) is more suited to high dc bus voltages than the six-switch alternative (six-switch CI). Operational and design details are described for the NPC-CI inverter using a three-limb inductor core, including practical considerations for the inverter construction and operation, 480 V/208 V inductor mass comparison between six- and twelve-switch topologies, natural voltage balancing of the split-capacitor dc link, and voltage stresses of the freewheel diodes. Improvements in machine performance are illustrated using two experimental test rigs: an unloaded 18 000-r/min 15-hp induction machine to illustrate improved harmonic quality when operating with a limited switching frequency and a high fundamental output frequency, and a loaded 2-hp utility speed induction machine to demonstrate transient performance. [ABSTRACT FROM AUTHOR]

A new scheme of single-phase transformerless grid-connected inverter is presented in this article. By employing the series–parallel switching conversion of the integrated switched-capacitor module in a packed unit, some attractive features for the proposed inverter can be obtained. Such promising features can be quantified as more than 97% overall efficiency for a wide range of output power, two-time boosting ability within a single-stage operation and almost total suppression of the leakage current through using the common grounding technique. In this case, a peak current controller strategy is used in order to trigger the gate of power switches and control both the active and reactive powers. Therefore, a tightly controlled current with an appropriate quality can be injected to the grid from a single source renewable energy resource. Operating procedure, design consideration, comparison study, and a 513 W built prototype results are also given to prove the correctness and feasibility of the proposed circuit. [ABSTRACT FROM AUTHOR]

A discontinuous pulse-width modulation (PWM) scheme is presented for a six-switch three-limb coupled inductor inverter. Three-level PWM phase output voltages are produced with a reduced switch count and reduced dv/dt stresses on loads and output filters. The PWM scheme described lowers the coupled inductor and semiconductor losses by lowering the inductor winding high-frequency current ripple using two techniques: 1) winding excitation flipping within each carrier cycle; and 2) the inductor magnetic flux is kept within the three-limb core, neglecting natural leakage, by avoiding switching states that produce common-mode voltage excitation of the three-limb inductor. To make best use of the nonstandard switching patterns produced, reference signals are preprocessed before being delivered to the PWM modules using only one carrier signal: representing an approach well suited for implementation in a low-cost digital signal processor. The digital output signals of each PWM module represent the desired switching states of each switch in the inverter. This approach contrasts with previous published work, where postprocessing of the PWM module output signals is necessary using digital logic circuitry, such as a field-programmable gate array. Experimental results, with inductor loss and inverter efficiency comparisons for different operating conditions, confirm that the three-phase six-switch inverter PWM patterns lower the high-frequency current ripple in the inductor windings and, hence, significantly lower the inverter losses and increase the power conversion efficiency. [ABSTRACT FROM PUBLISHER]

This letter presents a novel implementation of pulse width modulation that improves the quality of the line-to-line output voltages in interleaved multiphase voltage-source inverters (VSIs). In multiphase VSIs with n interleaved parallel-connected legs, the best single-phase output voltage is achieved when the carriers are evenly phase shifted. However, switching among nonadjacent levels can be observed at regular intervals in the line-to-line voltages, causing bad harmonic performance. With the proposed method, switching in the line-to-line voltages happens exclusively between adjacent levels. The modulator utilizes two sets of n evenly phase-shifted carriers that are dynamically allocated. Because of its generality, the proposed implementation is valid for any number of phases and any number of legs in parallel. A MATLAB/Simulink model has been set up for simulation purposes. Selected experimental results obtained from a three-phase VSI made up with two and three legs in parallel per phase are reported, confirming the enhancement attained with the proposed implementation. [ABSTRACT FROM AUTHOR]