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It is my great pleasure to introduce the Seventh Special Issue of the IEEE TRANSACTIONS ON ELECTRON DEVICES on Solid-State Image Sensors. Previous special issues were published in February 1976, August 1985, May 1991, October 1997, January 2003, and November 2009. During the six-year interval since the last special issue, significant changes have occurred in the field of solid-state image sensors. This is due, in particular, to the drive for low-power, high integration, compact imaging systems. Now that the speed of pixel shrinkage is slowing down, various new technologies are being developed to increase the functionality of the sensors, to make them more compact, to make them faster, to increase their dynamic range, etc. Papers reflecting these trends in the image sensor technology are well represented in this special issue. [ABSTRACT FROM AUTHOR]

A novel 3-D chip-level heterogeneous integration scheme for low cost and rapid pilot demonstration is proposed in this paper. The conventional Bumping fabrication is done at wafer level. However, due to the high cost of whole wafer, opting for chips with advanced technology node is a better alternative. Therefore, with the difficulties of the bumping process at chip level, 3-D heterogeneous integration by chip stacking faces challenges. This paper presents a novel heterogeneous integration platform by using electroless plating on chips and pillar bump on wafers before stacking. This integration platform can be applied to chip-to-chip or chip-to-wafer scheme when chips are fabricated from costly advanced technology node. [ABSTRACT FROM PUBLISHER]

This paper presents a comprehensive guide to co-design piezoelectric RF-micro-electromechanical system (MEMS) resonators and CMOS for enabling voltage-controlled MEMS oscillators (VCMOs) that harness the best benefits out of both platforms. The analysis, focusing on understanding different tradeoffs among the tuning range, power consumption, gain, and phase noise, is generic to any kind of piezoelectric resonators and specific for Colpitts VCMOs. As a result of this paper, the first VCMO based on the heterogeneous integration of a high-Q lithium niobate (LiNbO3) micromechanical resonator and CMOS has been demonstrated. A LiNbO3 resonator array with a series resonance at 171.1 MHz, a Q of 410, and an electromechanically coupling factor of 12.7% is adopted, while the TSMC 65-nm RF LP CMOS technology is used to implement the feedback and tuning circuitry with an active area of $220\times 70\,\,\mu \text{m}^{2}$. The frequency tuning of the VCMO is achieved by programming a binary weighted digital capacitor bank and a varactor that are both connected in series to the resonator. The best measured phase noise performance of the VCMO is −72 and −153 dBc/Hz at 1 kHz and 10-MHz offsets from 178.23- and 175.83-MHz carriers, respectively. The VCMO consumes a dc current of $60~\mu \text{A}$ from a 1.2-V supply while realizing a tuning range of 2.4 MHz (~1.4% fractional tuning range). Such VCMOs can be applied to enable ultralow power, low phase noise, and wideband RF signal synthesis for emerging applications in Internet of Things. [ABSTRACT FROM AUTHOR]

In this paper, we present the performance and imaging results of an integrated single-chip CMOS-microelectromechanical systems (MEMS) scanning microwave microscope (SMM). A systematic analysis for sensitivity improvement is described in detail. We first explain why it is important to have high sensitivity for this type of microscope and then propose a systematic method to analyze and design the entire structure for better sensitivity. For this, accurate lumped models are derived for each section of the system and comparisons are made between different designs. Furthermore, a new concept based on the quality factor of the individual sections is described to give the designer a tool to improve the sensitivity of individual sections without the need to simulate or model the entire system. A high-sensitivity measurement system is also explained. Finally some measurement results are presented. While the analysis presented in this paper is for CMOS-MEMS SMM, it is applicable to any type of SMM. [ABSTRACT FROM AUTHOR]

A miniaturized millimeter-wave substrate integrated waveguide (SIW) in IBM 130-nm digital CMOS process is presented in this paper. The footprint of the interconnect is reduced compared with previous works using the folding technique. A current-loop transition structure is proposed in this paper that is built inside the SIW interconnect and excites its TE10 mode with minimal area overhead. A simulation-based comparison of T-FSIW and other planar transmission line structures reveals that the T-FSIW interconnect shows a much higher resonant quality factor. A prototype waveguide is designed and fabricated to operate with a cutoff frequency of 175 GHz. Furthermore, the current-loop excitation is optimized for the frequency range of 180–220 GHz. Simulation and experimental data are used to confirm the proposed interconnect approach. [ABSTRACT FROM PUBLISHER]

This paper presents a tunable active bandpass filter (BPF) with adjustable transmission zeros (TZs) close to the passband for software-defined radio (SDR) applications. The RF front-end frequency selectivity is enhanced by the creation of TZs that also improve the out-of-band (OOB) input-referred third-order intercept point (IIP3). The filter is based on two-path signal cancellation and consists of a tunable BPF in parallel with two tunable bandstop filters. This combination ensures the correct amplitude and phase relationships across a wide tuning range to create adjustable TZs without sacrificing the gain of the passband. This paper presents in detail the design considerations and guidelines, as well as analysis of the filter performance in the presence of nonidealities such as parasitics and imperfect clock signal shape. The proposed filter is implemented with high- $Q~N$ -path filter blocks in a 65-nm CMOS process. The passband of the filter is tunable from 0.1 to 1.4 GHz with a 3-dB bandwidth of 9.8–10.2 MHz, a gain of 21.5–24 dB, a noise figure of 3–4.2 dB, and a total power consumption of 50–73 mW. TZs are created on both sides of the passband with a minimal offset of 25 MHz and are tunable across a 20-MHz range with up to a 60-dB rejection. The measured blocker 1-dB compression point is 8 dBm and the OOB IIP3 is 23 dBm. The reported filter provides a promising on-chip filtering solution for multistandard multifrequency SDR applications with improved interference mitigation capabilities. [ABSTRACT FROM AUTHOR]

After two decades of intensive development, 3-D integration has proven invaluable for allowing integrated circuits to adhere to Moore’s Law without needing to continuously shrink feature sizes. The 3-D integration is also an enabling technology for hetero-integration of microelectromechanical systems (MEMS)/microsensors with different technologies, such as CMOS and optoelectronics. This 3-D hetero-integration allows for the development of highly integrated multifunctional microsystems with small footprints, low cost, and high performance demanded by emerging applications. This paper reviews the following aspects of the MEMS/microsensor-centered 3-D integration: fabrication technologies and processes, processing considerations and strategies for 3-D integration, integrated device configurations and wafer-level packaging, and applications and commercial MEMS/microsensor products using 3-D integration technologies. Of particular interest throughout this paper is the hetero-integration of the MEMS and CMOS technologies. [2015-0158] [ABSTRACT FROM PUBLISHER]

Resonant body transistors (RBTs) are solid state, actively sensed microelectromechanical systems (MEMS) resonators that can be implemented in commercial CMOS technologies. With small footprint, high- $Q$ , and scalability to gigahertz frequencies, they form basic building blocks for radio frequency (RF) front-ends and timing applications. Toward the goal of seamless CMOS integration, this paper presents the design and implementation of phononic crystals (PnCs) in the back-end-of-line (BEOL) of commercial CMOS technologies with bandgaps in the gigahertz frequencies to be used for enhanced acoustical confinement in CMOS-RBTs. Lithographically defined PnC dimensions allow for bandgap engineering, providing flexibility in resonator design, and allowing for multiple frequencies on a single chip. The theoretical basis for analyzing generic PnCs is presented, with focus on the special case of implementing PnCs in CMOS BEOL layers. The effect of CMOS process variations on the performance of such PnCs is also considered. The analysis presented in this paper establishes a methodology for assessing different CMOS technologies for the integration of unreleased CMOS-MEMS resonators. This paper also discusses the importance of uniformity of the acoustical cavity in the nonresonant dimension and its effect on overall resonator performance. A PnC implementation in IBM 32-nm silicon on insulator (SOI) BEOL layers is demonstrated to achieve 85% fractional-bandgap \sim 4.5$ -GHz frequency. With better energy confinement, the proposed CMOS-RBTs achieve a quality factor Q$ of 252, which corresponds to 8\times . This paper concludes with a discussion of the properties required of a CMOS technology for high performance RBT implementation. [2014-0364] [ABSTRACT FROM PUBLISHER]

This paper presents a power amplifier (PA) topology to improve the back-off efficiency and the linearity of millimeter-wave (mm-wave) PAs without area overhead. In this paper, an asymmetrical series power combiner with LC tuning circuits is proposed to mimic the Doherty operation. Due to high back-off efficiency and high linearity behavior, the proposed Doherty topology well suits for E-band communication applications. Two transformer-based E-band PAs are designed and measured to demonstrate the proposed mm-wave Doherty concept. The first implementation achieves 16.2-dBm output power with a P1dB of 15.2 dBm using a 0.9-V supply. The second implementation demonstrates 21-dBm output power with a power-added efficiency (PAE) of 13.6% at a 1.5-V supply. The PAE at 6-dB power back-off is still as high as 7%. [ABSTRACT FROM AUTHOR]

In this paper, a two-stage broadband CMOS stacked FET RF power amplifier (PA) with a reconfigurable interstage matching network is developed for wideband envelope tracking (ET). The proposed RF PA is designed based on Class-J mode of operation, where the output matching is realized with a two-section low-pass matching network. To overcome the bandwidth (BW) limitation from the high- Q interstage impedance, a reconfigurable matching network is proposed, allowing a triple frequency mode of operation using two RF switches. The proposed RF PA is fabricated in a 0.32-\mu\m silicon-on-insulator CMOS process and shows continuous wave (CW) power-added efficiencies (PAEs) higher than 60% from 0.65 to 1.03 GHz with a peak PAE of 69.2% at 0.85 GHz. The complete ET PA system performance is demonstrated using the envelope amplifier fabricated on the same process. When measured using a 20-MHz BW long-term evolution signal, the overall system PAE of the ET PA is higher than 40% from 0.65 to 0.97 GHz while evolved universal terrestrial radio access adjacent channel leakage ratios are better than -\33 dBc across the entire BW after memoryless digital pre-distortion. To our knowledge, this study represents the highest overall system performance in terms of PAE and BW among the published broadband ET PAs, including GaAs HBT and SiGe BiCMOS. [ABSTRACT FROM AUTHOR]

Acoustic resonators, such as thin-film solidly mounted resonators (SMRs) and silicon microelectromechanical systems have been used widely in commercial and research RF communication circuits to implement high-Q oscillators and highly selective filters. Monolithic integration is a promising solution to address the growing demand for such components while continuing the aggressive miniaturization of radios. In this paper, we demonstrate successful monolithic SMR-CMOS co-integration by building a high-Q SMR atop a standard 65-nm CMOS substrate using a custom die-level fabrication process. The approach takes advantage of features in the back-end-of-line to deliver the surface smoothness required for fully supported mechanical resonators, which was not possible using traditional process approaches. This paper marks the first demonstration of SMR integration on 65-nm CMOS. The CMOS die used is more than 400% smaller in area than those in the previous die-level demonstrations of monolithically integrated piezoelectric resonators on CMOS. [2016-0192] [ABSTRACT FROM PUBLISHER]

Dynamic and static current injection methods to improve the linearity of a current commutating mixer are investigated and a double-balanced CMOS mixer (DBM) providing high linearity is presented in this paper. A cross-coupled pair is used in the IF stage of the mixer to dynamically inject current into the mixer to provide a high linearity. The proposed DBM was fabricated using a standard 130-nm CMOS process and was tested on-wafer. The double-balanced mixer delivers 10-dB conversion gain, 9.5-dBm third-order intercept point, and input P1\text {dB} of −2.4 dBm. RF bandwidth of the proposed mixer is 6 GHz, covering 0.5–6.5 GHz with an IF bandwidth of 300 MHz. RF to IF and LO to IF isolation are also better than 59 dB in the whole frequency band. The circuit uses an area of 0.015 mm2 excluding bonding pads and draws 4.5 mW from a 1.2 V supply. [ABSTRACT FROM AUTHOR]

This paper presents a nonlinear Q-switching impedance (NLQSI) technique for picosecond pulse radiation in silicon. A prototype chip is designed with four NLQSI-based impulse generation channels, which can produce picosecond pulses with a reconfigurable amplitude. An on-chip impulse-coupling scheme combines the outputs from four channels and delivers the combined signal to an on-chip antenna. In addition, an asynchronous optical-sampling measurement system is used to characterize the radiated picosecond pulses in the time domain. The prototype chip can radiate 4-ps pulses with an SNR > 1 bandwidth of 161 GHz. Furthermore, pulse amplitude modulation is experimentally demonstrated. The prototype chip is fabricated in a 130-nm SiGe BiCMOS process technology with a die area of 1 mm2. [ABSTRACT FROM PUBLISHER]

Design and analysis of low-phase-noise low-jitter subharmonically injection-locked voltage-controlled oscillator (VCO) with frequency-locked loop (FLL) self-alignment technique is presented in this paper using 90-nm CMOS process. The issue of the narrow locking range for the subharmonically injection-locked VCO (SILVCO) can be resolved over the variations, especially for high subharmonic number and millimeter-wave band, since the control voltage is adaptively adjusted using the proposed innovative method to refer to the subharmonic input frequency. A theoretical model of the SILVCO with FLL self-alignment technique is addressed for the design consideration and phase noise evaluation. With a subharmonic number of 16, the operation frequency of the proposed $K$ -band circuit is from 24 to 26.1 GHz. The measured minimum phase noise at 1-MHz offset and jitter integrated from 1 kHz to 40 MHz are −114.3 dBc/Hz and 56.6 fs, respectively. As the temperature is from 20 °C to 70 °C, the measured deviations of output power, phase noise, and jitter are within 2 dB, 3 dB, and 67 fs, respectively. This paper demonstrates excellent performance and good robustness, and it can be compared with the previously reported state-of-the-art clock generators in silicon-based technologies. [ABSTRACT FROM PUBLISHER]

In this paper, we develop a statistical model for random telegraph noise (RTN) related low-frequency noise (LFN). With our proposed model, one can calculate the expected value and the variability of the noise as a function of bias and device parameters. We clarify why the variability of RTN/LFN does not follow a 1/ $\surd $ area dependence. The model explains the effect of the halo implanted regions on the LFN statistics and the large variability of long channel devices found under certain bias conditions, which can be as large as that of short channel devices. We show that the LFN of n-channel and p-channel MOSFETs can be described by the same mechanism. From our results, we derive that the trap density of the p-channel device is a strongly varying function of the Fermi level, whereas for the n-channel the trap density can be considered constant. We validate the model through numerous experimental results from different CMOS nodes, down to 40 nm. We also demonstrate that the noise, and its variability, found in our measurements can be modeled using reasonable physical quantities. [ABSTRACT FROM AUTHOR]

We derive analytically expressions for the probability distribution of the propagation delay time of logic signals through a CMOS inverter when the inverter power supply voltage $V_{{\text{dd}}}$ (more precisely, gate voltage $V_{{\text{GS}}}$) is itself probabilistic for some reason (e.g., system noise or a random external electromagnetic disturbance). Since the propagation delay time is a function of the value of $V_{{\text{dd}}}$ , then some values of $V_{{\text{dd}}}$ may produce values of the inverter propagation delay time that cause the circuit in which the inverter resides to malfunction (e.g., by resulting in an inverter delay time value not conforming with the delay time margins for that circuit). Based upon the derived inverter propagation delay time probability distribution, we then derive a probability for the malfunction of a circuit containing a single inverter subject to such a stochastic $V_{{\text{dd}}}$. In this paper, we present no discussion of the application of our formalism to example probability density functions for $V_{{\text{dd}}}$ ; we rectify this situation by presenting three detailed such examples in a companion paper in this journal. [ABSTRACT FROM AUTHOR]

Domain wall nanomagnet (DWNM)-based devices have been extensively studied as a promising alternative to the conventional CMOS technology in both the memory and logic implementations due to their non-volatility, near-zero standby power, and high integration density characteristics. In this paper, we leverage a physics-based model of a DWNM device to design a highly scalable current-mode majority gate to achieve a novel one bit full-adder (FA) circuit. The modeled DWNM specifications are calibrated with the experimentally measured data. The functionality of the proposed DWNM-based FA (DWNM-FA) is verified using a SPICE circuit simulator. The detailed analysis and the calculations have been performed to realize the proposed DWNM-FA delay and power consumption corresponding to the various induced input currents at different operating temperatures. The power-delay product of DWNM-FA is examined to tune the operation within the optimum induced input current region to obtain desired power-delay requirements over a range of 200 \mu \textA to 1 mA at temperatures from 298 to 378 K. Finally, the comparison results exhibit 52% and 49% area improvement as well as 41% and 31% improvement in device count complexity over CMOS-based and magnetic tunnel junction-based FA designs, respectively. [ABSTRACT FROM PUBLISHER]

In this paper, Ge nanowire (NW) CMOS devices and circuits are analyzed in detail. Various experiment splits are studied, including device geometry parameters such as the channel lengths ( L\mathrm{ ch} ) from 100 to 40 nm, a NW height ( H\mathrm{ NW} ) of 10 nm, the NW widths ( W\mathrm{ NW} ) from 40 to 10 nm, and the dielectric equivalent oxide thicknesses (EOTs) of 2 and 5 nm, and four types of device operation modes of accumulation mode (AM) and inversion mode (IM) n-type MOSFETs and p-type MOSFETs. Benefited from the NW structure with scaled EOT, subthreshold swing (SS) as low as 64 mV/dec and maximum transconductance ( g\max ) as high as 1057~\mu \textS/\mu \textm are obtained on the Ge NW nMOSFETs. The NW pMOSFETs are also realized on the same common substrate. Furthermore, hybrid Ge NW CMOS with AM nMOSFET and IM pMOSFET is demonstrated for the first time on a Si substrate. The highest maximum voltage gain reaches 54 V/V in the Ge NW CMOS inverters. [ABSTRACT FROM PUBLISHER]

This paper presents a Ternary Content-addressable Memory (TCAM) design which is based on the use of floating-gate (flash) transistors. TCAMs are extensively used in high speed IP networking, and are commonly found in routers in the internet core. Traditional TCAM ICs are built using CMOS devices, and a single TCAM cell utilizes 17 transistors. In contrast, our TCAM cell utilizes only two flash transistors, thereby significantly reducing circuit area. We cover the chip-level architecture of the TCAM IC briefly, focusing mainly on the TCAM block which does fast parallel IP routing table lookup. Our flash-based TCAM (FTCAM) block is simulated in SPICE, and we show that it has a significantly lowered area compared to a CMOS based TCAM block, with a speed that can meet current (~400 Gb/s) data rates that are found in the internet core. [ABSTRACT FROM AUTHOR]

In this paper, we report the development of a high- k /metal gate stacking process to reduce the effective gate resistance, and circuit level validation results in 28-nm gate first integrated high- k /metal gate CMOS devices. To achieve this, millisecond annealing was adopted and the silicon (Si) gate and TiN gate electrode thicknesses were controlled. The recrystallized poly-Si gate by millisecond annealing improved the performance of the ring oscillator (RO) by 15% and the minimum operating voltage ( V\min ) of the high-frequency test pattern (HFTP) by 34 mV. The poly-Si gate improved the uniformity of the boron concentration and suppressed localized low doping area at the bottom of the gate. When the Si gate thickness was reduced by 10 Å with respect to the reference (POR) value, the performance of the RO improved by 5% and V\min of HFTP improved by 20 mV due to the shorter boron diffusion distance. A 10- Å thicker TiN gate electrode improved V\min of HFTP by 30 mV, since the thicker TiN reduced the TiN/Si gate interface resistance. [ABSTRACT FROM AUTHOR]

In this paper, a novel CMOS single-photon avalanche diode (SPAD) is presented, and the device is designed using a vertical p-i-n diode construction. The p-i-n diode with a wide depletion region enables a low-noise operation. The proposed design achieves dark count rates of 1.5 cps/ \mu \textm^2 at 11 V excess bias, while the photon detection probability (PDP) is greater than 40% from 460 to 600 nm. Through the operation at very high excess bias voltages, it is possible to reach the PDP compression point where sensitivity to the breakdown voltage is low, thus ensuring high PDP uniformity; this feature makes it, especially, suitable for multimegapixel SPAD arrays. [ABSTRACT FROM AUTHOR]

This paper presents a time-of-flight (TOF) range imager with high-range resolution. The range imager employs a TOF measuring technique using an impulse photocurrent response and a high-speed lock-in pixel based on a draining-only modulation. To address a skew problem in a 2-D array of the pixels, a column-wise gating-clock skew calibration was implemented. Each pixel has an in-pixel buffer and decoupling capacitor to reduce row-wise skew. A test-implemented imager has $132 \times 120$ effective pixels. The skew calibration circuit successfully reduce the skew from 173 to 8 psrms. The range resolution was achieved to be 0.25 mm with a 32-mm range, which corresponds to a 1.7-ps time resolution. [ABSTRACT FROM AUTHOR]

This paper presents a pathfinder binary image sensor for exploring low-power dissipation needed for future implementation of gigajot single-bit quanta image sensor (QIS) devices. Using a charge-transfer amplifier design in the readout signal chain and pseudostatic clock gating units for row and column addressing, the 1-Mpixel binary image sensor operating at 1000 frames/s dissipates only 20-mW total power consumption, including I/O pads. The gain and analog-to-digital converter stages together dissipate 2.5 pJ/b, successfully paving the way for future gigajot QIS sensor designs. [ABSTRACT FROM AUTHOR]

Based on the thermionic emission theory, a charge transfer model has been developed which describes the charge transfer process between a pinned photodiode and floating diffusion (FD) node for CMOS image sensors. To simulate the model, an iterative method is used. The model shows that the charge transfer time, barrier height, and reset voltage of the FD node affect the charge transfer process. The corresponding measurement results obtained from two different test chips are presented in this paper. The model also predicts that other physical parameters, such as the capacitance of the FD node and the area of the photodiode, will affect the charge transfer. Furthermore, the model can be extended to explain the pinning voltage measurement method and the feedforward effect. [ABSTRACT FROM AUTHOR]

This paper presents a low-power column-parallel inverter-based cyclic analog-to-digital converter (ADC) for CMOS image sensor readout circuit. By partially floating the capacitors inside the multiply digital-analog-converter during the least significant bit (LSB) quantization, the amplifier load capacitance could be significantly scaled down, which allows much higher settling speed and shorter cycle period. Since the signal-to-noise ratio for LSB cycle is relaxed due to the residual amplification, the proposed capacitance scaling only contributes ignorable input-referred quantization noise. Using the proposed techniques, a cyclic ADC can operate under 50% power consumption without suffering conversion rate, noise performance, and linearity. A 12-b quantization resolution test chip is fabricated using the TSMC 0.18- \mu \textm technology with 110 column-parallel ADC channels and 10.08- \mu \textm \times 750 - \mu \textm column pitch. The 3.5/−2 LSBs integral nonlinearity and 10.1-b effective-number-of-bit are measured under 2- \mu \texts sampling rate with 120- \mu \textW power consumption per channel. [ABSTRACT FROM AUTHOR]

Transistor count minimization is an important goal as very-large-scale integration technology approaches its technical and physical limits. In this paper, we present a computer-aided design synthesis tool that tries to minimize the number of transistors required to implement a given multiple-output logic function. The proposed transistor-level synthesis approach goes beyond the traditional series-parallel design style and allows for extensive bridging. It starts from a sum-of-products expression for each output, allowing also for don’t care terms, and produces a transistor network with a small number of transistors to implement all outputs jointly under a user-specified bound on the number of transistors in series to avoid long charge/discharge paths. Experimental results on previously examined multioutput functions and case studies (full adder, Gray/binary counter, and seven-segment display) demonstrate the benefit of the approach. [ABSTRACT FROM PUBLISHER]

In this paper, an inverter logic gate has been successfully designed based on the previously proposed side-contacted field-effect diodes (S-FEDs). Effect of the reservoir thickness on the S-FED performance is investigated, and then the output characteristics of the S-FED-based inverter are studied and compared with those of the existing CMOS technology. The S-FED performance evaluation is performed in terms of important figures of merit for logic application in various reservoir thicknesses, including transconductance, intrinsic gate delay time, energy delay product, and subthreshold slope. The numerical results demonstrate that the optimum reservoir thickness is 7 nm, and the threshold voltage can be controlled by reservoir thickness. Mixed-mode simulations also indicate that, in the design of an inverter utilizing S-FEDs, the delay and the power dissipation of the logic gate are reduced. These results indicate that the S-FED can be an interesting candidate for designing low-power and high-speed logic gates. [ABSTRACT FROM PUBLISHER]

The gastro-intestinal (GI) tract is a very important part of the human digestive system but remains largely inaccessible for unobtrusive monitoring. Ingestible electronic devices are a very interesting concept to address this need. This paper discusses the current state of ingestible electronic devices and explores the potential they hold to provide unprecedented insight by measuring several aspects of the complex bio-chemical processes that happen in the GI tract in real-time. This will require novel sensor technology capable of measuring relevant markers with adequate specificity and accuracy. In order to be able to scale this functionality down to a form factor of an easily digestible pill, ultra-low-power wireless interface electronics are needed. This poses certain challenges and innovation opportunities related to sensing, wireless communication and powering to enable the next generation of ingestible electronic devices. [2020-0164] [ABSTRACT FROM AUTHOR]

In this paper, CMOS wafer level ring oscillator frequency variability improvement >40% is demonstrated by either spatial source/drain activation or ion implantation super scan in FinFET technology. Yield improvement (up to 17%) is verified with better within wafer uniformity and with no intrinsic device performance degradation. Furthermore, the combination of super scan and spatial source/drain activation is suggested for optimized variability improvement benefits from individual device type uniformity tuning (super scan) and all device type uniformity tuning (from spatial S/D activation). [ABSTRACT FROM AUTHOR]