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A hybrid switched-capacitor/interleaved boost converter able to provide a high voltage gain and to cancel the input current ripple at a preselected duty cycle was recently presented in the literature. This paper extends that work by proposing an optimized switching strategy for operating conditions at other values of duty cycle. The switching strategy effect on the converter's voltage gain and input current ripple is quantified and compared against the performance under the conventional switching strategy. The approach is validated in the laboratory through hardware prototyping. [ABSTRACT FROM PUBLISHER]

This paper presents a new six-level flying capacitor based (FC-based) multilevel converter with one dc source and the capability of operating in all power factors and modulation indexes. Multilevel converters with one dc voltage source are attractive in many applications as they do not need rather expensive and bulky multiwinding input transformer connection at the dc side. On the other hand, not all classic multilevel converters with one dc source can produce any desirable number of output voltage levels at all power factors and/or modulation indexes. In this paper, a hybrid structure is proposed in which six voltage levels can be realized at the ac terminals. The modulation technique and the control strategy for the FC voltage balancing are presented. To show the advantages of the proposed converter, different performance criteria, such as switch count and rating, the size of capacitors, switching frequency, and power losses, are compared with other existing six-level topologies. The results indicate that the proposed structure is superior to other six-level converters from different standpoints. Simulation results are used to further evaluate the performance of the proposed converter. A laboratory-type experimental setup is used to validate the theoretical results. [ABSTRACT FROM AUTHOR]

Multilevel cascaded H-bridge converters have become a mature technology for applications where high-power medium ac voltages are required. Normal operation of multilevel cascaded H-bridge converters assumes that all power cells have the same dc voltage, and each power cell generates the same voltage averaged over a sampling period using a conventional phase-shifted pulse width modulation (PWM) technique. However, this modulation method does not achieve good results under unbalanced operation per H-bridge in the power converter, which may happen in grid-connected applications such as photovoltaic or battery energy storage systems. In the paper, a simplified mathematical analysis of the phase-shifted PWM technique is presented. In addition, a modification of this conventional modulation method using variable shift angles between the power cells is introduced. This modification leads to the elimination of harmonic distortion of low-order harmonics due to the switching (triangular carrier frequency and its multiples) even under unbalanced operational conditions. The analysis is particularized for a three-cell cascaded H-bridge converter, and experimental results are presented to demonstrate the good performance of the proposed modulation method. [ABSTRACT FROM PUBLISHER]

The noninverting buck–boost converter has attracted significant attention in the photovoltaic (PV) module integrated application, as it offers high efficiency while maintaining a low cost and a simple topology. When this converter is employed, special care must be taken at the transition between buck and boost operating modes, as a dead-zone in the voltage transfer function can cause abrupt perturbations in the controlled voltage, decreasing the regulation quality and ultimately lowering the power conversion efficiency. In this paper, a new dead-zone compensation technique is proposed with the scope of smoothing the transition between operating modes, eliminating the voltage ripple and improving the regulation performance, while maintaining high efficiency. The converter under analysis is studied together with its gate driving circuit, which is based on a bootstrap capacitor power supply for the high-side switches. The proposed dead-zone compensation technique is deduced by using the principle of maintaining the ideal voltage gain function across the converter operating range. The technique is analyzed, implemented and tested on a purposely built PV module integrated noninverting buck–boost converter. The experiments reveal a sensible improvement of the voltage regulation during mode transition, confirming the effectiveness of the proposed technique and its fitness for the PV application. [ABSTRACT FROM AUTHOR]

This paper addresses the inverter nonlinearity of a three-level T-type inverter. The main causes of the nonlinearity are pulse shaping, pulse skipping due to narrow pulses for the dead time, and voltage drop of the switching devices. Although the same causes have existed in two-level inverters, the pulse skipping phenomenon and results are quite different in the case of the three-level T-type inverter. The effects of pulse shaping and skipping have been investigated and discussed. In addition, the voltage drop of the switching devices has been considered in conjunction with the conduction path of the T-type inverter. Compensation methods based on the pulse width modulation (PWM) of T-type inverter to alleviate the inverter nonlinearity have been proposed from research results. The proposed methods could be easily implemented by adding appropriate offset voltages to the voltage references of the inverter in PWM. Furthermore, a neutral voltage balancing method of a three-level T-type inverter has been proposed in conjunction with the proposed PWM methods using offset voltage. Through extensive experimental tests, the fifth- and seventh-harmonic components of the current are conspicuously reduced along with the even harmonics. The neutral voltage of the inverter can be balanced effectively with the proposed offset voltage adjustments as well. [ABSTRACT FROM AUTHOR]

This paper proposes a multilevel series compensator (MSC) to deal with voltage sags/swells, harmonic compensation, or reactive power compensation. Such a device can be considered as a dynamic voltage restorer or a series active power filter (Series-APF). The MSC can improve the power quality of loads located in stiff systems. The configuration is based on three-phase bridge (TPB) converters connected by means of cascaded single-phase transformers. This arrangement permits the use of a single dc-link. A generalization for $K$ -stages in which $K$ -transformers are coupled with $K$-TPB converters is presented. The topology permits generating a high number of levels in the voltage waveforms with a low number of power switches in comparison with a classic topology. The multilevel waveforms are generated by the converters through a suitable pulsewidth modulation (PWM) strategy that takes into consideration the transformer turns ratios. Modularity and simple maintenance make the proposed MSC an attractive solution compared with some conventional configurations. Model, PWM strategy, and overall control are discussed in this paper. Simulation and experimental results are presented as well. [ABSTRACT FROM PUBLISHER]

In an asymmetrical pulse-width-modulated half-bridge (APWM HB) series resonant converter, an auxiliary LC network is provided for ensuring zero-voltage switching (ZVS) over a wide range of line and load variations. However, it comes at the cost of increased number of components and reduced efficiency and reliability. This paper presents a novel design methodology for the standard APWM HB resonant topology, which uses the magnetizing current and eliminates the need for extra components. The converter with the proposed design methodology operates at the resonant frequency of the tank and features load-independent ZVS for a wide range of input voltage variation with minimal magnetizing current. Empirical formulae are derived to design the resonant network and the magnetizing inductance of the high-frequency transformer systematically in a flowchart-based manner. The proposed design is validated by using simulations as well as experiments and is compared with a reference APWM HB series resonant converter design that uses an auxiliary LC circuit for ZVS. Two separate experimental prototypes of the two converters rated for 30 W, 48 V/5 V with a switching frequency of 500 kHz were built and tested in the laboratory. It was found that the converter with the proposed design methodology, apart from having lower component count, is about 3% more efficient than the reference topology at the rated power. [ABSTRACT FROM PUBLISHER]

Cascaded converters are adopted in many power systems to manage sources and loads at different voltage levels simultaneously. DC bus capacitor is one of the key components in these converters due to its energy storage and fast response capabilities. However, the ripple current through the capacitor will influence its lifetime and the overall efficiency of the converter. Previous studies showed that the capacitor current of ac systems is optimized when the duty cycles are synchronized under in phase or antiphase condition. In this paper, the bus capacitor ripple current of cascaded two-stage converters for dc systems with different combinations of duty cycles is analyzed. It is found that the optimum capacitor current ripple varies depending on the values of individual duty cycles and the phase-shift angle between them. By properly adjusting the phase shift, the capacitor RMS current value can be reduced without affecting the converter normal operation or the need for extra sensing circuits, hence improving the energy conversion efficiency and prolonging the capacitor lifetime with relatively simple implementation. To illustrate, a case study of a two-stage dc/dc converter is carried out. A laboratory prototype converter confirmed a maximum efficiency improvement of 2.8% if the phase shift is adjusted properly when compared to the same converter with the worst case phase-shift angle. [ABSTRACT FROM AUTHOR]

An open-winding power conversion system with two conventional six-switch voltage-source converters (VSC) affords operation with a lower volt-ampere (VA) rating of each device for a given power rating, as well as a degree of fault tolerance. The disadvantages of such a configuration include a higher total device VA rating and increased conduction loss as compared to a single Y/Δ-connected VSC. In certain ac-dc applications, such as telecommunications, wind, and aerospace generator drives, it is desired to have regulated input currents and output voltage, but regenerative operation is either not required or prohibited. For such applications, an alternative open-winding power converter is proposed in this paper where half-controlled converter (HCC) is employed at each end of an open-winding structure. The resultant total switch count and total VA rating are reduced by half, compared to using full bridges. Besides, the basic advantages of an open-winding configuration, use of HCCs also guarantees immunity to dc-bus shootthrough and simplifies the gate drive circuit. The total VA rating of the proposed topology is found to be 42% less than a six-switch VSC. The operating principle, control method, and analysis with simulation and experimental results of the proposed topology in both a grid-tied rectifier application and a PM generator application are illustrated in this paper. [ABSTRACT FROM AUTHOR]

Pulse-width-modulated (PWM) converters have been widely applied for power processing, and they are typically the stems of other types of converters, such as quasi-resonant, Z-source, and switched-inductor hybrid converters. Development of PWM converters has been spanning over a century, starting from the buck converter. The well-known PWM converters include buck, boost, buck–boost, Ćuk, single ended primary inductive converter (SEPIC), zeta, Z-source, quasi-Z source, etc. Many attempts have been proposed to develop these converters based mostly on canonical cell concepts and by introducing extra LC filters to the cells. This paper presents an enhancement to the layer and graft schemes by introducing the ideas of dc voltage/current offsetting, capacitor/inductor component splitting, diode grafting, and inverse operation of PWM converters. The PWM converters, which can be operated in continuous conduction mode (CCM) or discontinuous conduction mode (DCM), therefore can be synthesized systematically according to decoded transfer gains. Decoding and synthesizing PWM converters uniquely bridge transfer gains to converter topologies and provide readers a comprehensive understanding of PWM-converter evolution from the original converter, the buck converter. Additionally, in this paper, the Ćuk, SEPIC, and zeta converters all with the same transfer gain of $D/(1 - D)$ are proved to be equivalent to the buck–boost converter with an extra LC filter. For further illustrating the proposed approaches, various types of Z-source converters, switched-capacitor/switched-inductor hybrid converters, and a single-stage interleaved converter are reviewed, and new PWM converters are developed. [ABSTRACT FROM AUTHOR]

This paper revisits the switched flow graph (SFG) technique. A general and unified equivalent SFG model of a three-terminal switcher encountered in regular and tapped inductor converters operating in the continuous conduction mode is proposed. The model can be applied to most PWM topologies and facilitates construction of a complete flow graph of a given converter. The approach can be helpful in theoretical analysis and derivation of analytical expressions of converter's small-signal transfer functions. The suggested methodology extends the previously proposed SFG analysis technique and alleviates the principal difficulties involved. Furthermore, the approach is straightforward and expeditious. Application guidelines and examples are presented and compared to simulation and earlier theoretical results. [ABSTRACT FROM PUBLISHER]

In this paper, a pulsewidth modulation (PWM) plus secondary-side phase-shift (SSPS) controlled full-bridge three-port converter (FB-TPC) is proposed for a renewable power system, which is derived by integrating two interleaved buck/boost circuits (IBBC) and a SSPS full-bridge converter (FBC), to interface the energy source, energy storage element, and output load simultaneously. The two switching legs are shared by the IBBC and FBC, which improves the active devices sharing ratio and power density. With PWM plus SSPS control scheme, decoupled power control can be realized and the converter can achieve wide input voltage range power conversion. In addition, zero-voltage switching (ZVS) of both the primary and secondary switches are achieved in a wide range. Furthermore, the circulating current can be greatly eliminated, which helps to reduce conduction losses. Moreover, the voltage stresses on the secondary rectifier are effectively suppressed since the power switches and diodes are clamped to output voltage. The operation principles, output characteristics, ZVS performances, and control strategy are analyzed in detail. Experimental results of a 600-W prototype are provided to verify the effectiveness and the advantages of the proposed converter. [ABSTRACT FROM PUBLISHER]

In this paper, three generalized configurations of three-phase pulsewidth modulated (PWM) rectifiers are presented. They are composed of cascaded cells, each formed by a three-phase bridge of switching devices and a three-phase transformer to cascade the cells and isolate the load from the power source. One configuration is bidirectional, whereas the other two are unidirectional alternatives that replace power switches for diodes in some legs. The turns ratios of transformers from each cell are designed in order to provide the required gain and number of levels in the inverted multilevel voltage, enhancing power quality while attending requirements for proper operation in each case. Configurations with two and three cells are compared by means of simulations between themselves and with three conventional three-phase PWM rectifiers: the two-level insulated gate bipolar transistor bridge and the multilevel neutral point clamped (NPC) bridge and NPC H-bridge. Many degrees of asymmetry between the transformers in each cell, determined by the turns ratios, are considered to evaluate their impact on the topologies with relation to performance and cost. It is shown that proposed multilevel rectifiers present lower harmonic distortion, semiconductor losses, and switching stress, and some options with intermediate asymmetry are considered as good alternatives to the most asymmetrical cases. Experimental results are also provided for configurations with two cells, to demonstrate their lower harmonic distortion and power losses compared to the conventional isolated two-level PWM rectifier. [ABSTRACT FROM AUTHOR]

This paper presents a single-phase transformerless grid-connected photovoltaic converter based on two cascaded full bridges with different dc-link voltages. The converter can synthesize up to nine voltage levels with a single dc bus, since one of the full bridges is supplied by a flying capacitor. The multilevel output reduces harmonic distortion and electromagnetic interference. A suitable switching strategy is employed to regulate the flying-capacitor voltage, improve the efficiency (most devices switch at the grid frequency), and minimize the common-mode leakage current with the help of a novel dedicated circuit (transient circuit). Simulations and experiments confirm the feasibility and good performance of the proposed converter. [ABSTRACT FROM PUBLISHER]

This paper presents the hybrid seven-level cascaded active neutral-point-clamped (ANPC)-based multilevel converter. The converter topology is the cascaded connection of a three-level ANPC converter and an H-bridge per phase. The voltage of the H-bridge is actively maintained to the required level through selection of the switching states of the converter. The topology is operated under selective harmonic elimination pulsewidth modulation (SHE-PWM), maintaining the switching frequency of the converter to a minimum. The operating principles, voltage balancing methods, and limitations of the converter are analyzed together with extensive simulation results of the topology. Experimental results from a low-power laboratory prototype are presented that verify the operation of the hybrid converter under SHE-PWM. [ABSTRACT FROM PUBLISHER]

Five-level hybrid-clamped (5L-HC) converter is a newly proposed topology which is suitable for high-performance medium-voltage high-power conversions without switches directly connected in series. The critical issue of this converter is that two flying capacitor voltages of each phase and two neutral-point potentials of the dc-link need to be balanced. This paper presents a decoupled voltage balancing method for this 5L-HC converter based on modified phase-shifted pulse width modulation (PS-PWM) and optimal zero-sequence voltage injection. The voltages across the central dc-link capacitor and two flying capacitors are balanced first by adjusting the width of four PWM signals. Second, the relationship between the neutral-point currents and the output phase voltage is studied and the upper and lower dc-link capacitor voltages are balanced by zero-sequence voltage injection. Both steady-state and dynamic-state simulation and experimental results are presented to confirm the validity of this method. [ABSTRACT FROM AUTHOR]

Four-level hybrid-clamped (4L-HC) inverter is a newly proposed topology which is suitable for high-performance medium-voltage drives. Each phase of this topology consists of eight switches and a flying capacitor and the dc-link is split into three parts by two neutral points. In order to ensure the topology operating properly, the voltages across the flying capacitors and three dc-link capacitors should be controlled and maintain balanced at their nominal values. This paper presents a decoupled voltage balancing method for this 4L-HC inverter, including the voltage balancing of dc-link capacitors and flying capacitors. A modified phase-shifted pulse-width modulation method is used to regulate the voltages of flying capacitors and the central dc-link capacitor. The relationship between the neutral-point currents and the output voltage is studied and the upper and lower dc-link capacitor voltages are balanced by injecting an optimum zero-sequence voltage. Simulation and experimental results are presented to verify the validity of this method. [ABSTRACT FROM AUTHOR]

Photovoltaic systems technological development is driven by the request for higher efficiency and safety. These concerns influence also the choice of the power converter stage. Several topologies have been proposed and many of them are available commercially. Among them, the neutral point clamped (NPC) and derived topologies offers high efficiency, low leakage current, and low EMI. However, one main disadvantage of the NPC inverter is given by an unequal distribution of the losses in the semiconductor devices, which leads to an unequal distribution of temperature that can affect lifetime. By using the active NPC (ANPC) topology, where the clamping diodes are replaced by bidirectional switches, the power losses distribution problem is alleviated. The modulation strategy is a key issue for losses distribution in this topology. In this paper, two known strategies are discussed and a new PWM strategy, namely the adjustable losses distribution is proposed for better losses distribution in the ANPC topology. Simulations and experimental results help in evaluating the modulation strategies. [ABSTRACT FROM AUTHOR]

Fast fault detection and reconfiguration of power converters is necessary in electrical drives to prevent further damage and to make the continuity of service possible. On the other hand, component minimized converters may provide the benefits of higher reliability and less volume and cost. In this paper, a new fault-tolerant converter topology is studied. This converter has five legs before the fault occurrence, and after fault detection the converter continues to function with four legs. A very fast fault detection and reconfiguration scheme is presented and studied. Simulations and experimental tests are performed to evaluate the structure requirements, the digital reconfigurable controller, and fault detection scheme. For experimental tests, the control and the fault detection and reconfiguration schemes are implemented on a single field-programmable gate array (FPGA) chip. Experimental and simulation results show the effectiveness of the proposed fault-tolerant topology and its FPGA-based control. [ABSTRACT FROM PUBLISHER]

Flying-capacitor converters (FCCs), like most multilevel converter topologies, require a balancing mechanism of the capacitor voltages. FCCs feature natural voltage balancing when a special modulation technique is used. The classic methods, such as phase-shifted pulse width modulation (PS-PWM), result in very slow balancing for some duty-ratio ranges. Previous work has shown that for a single-leg five-level FCC, one time constant is infinite for a zero desired output voltage. In this paper, a modified PS-PWM scheme for a single-leg five-level FCC is presented, which results in faster balancing over the total duty-ratio range. The modified PS-PWM scheme is studied, resulting in an averaged voltage-balancing model. This model is verified using simulations and experiments. The modified PS-PWM scheme solves the slow-balancing problems of the normal PS-PWM method for odd-level FCCs, while maintaining the passive control property, and it provides a self-precharge capability. [ABSTRACT FROM AUTHOR]

A modified single-phase quasi-Z-source ac-ac converter is proposed in this paper. The proposed converter has the main features in that the output voltage can be bucked or boosted and be both in-phase and out-of-phase with the input voltage. The input voltage and output voltage share the same ground, the size of a converter is reduced, and it operates in a continuous current mode. A safe-commutation strategy for the modified single-phase quasi-Z-source ac-ac converter is used instead of a snubber circuit. The operating principles and a steady-state analysis are presented. A laboratory prototype, tested using a resistive load, a passive load, and a nonlinear load, was constructed that used an input voltage of 70 Vrms /60 Hz in order to verify the performance of the modified single-phase quasi-Z-source ac-ac converter. The experimental results verified that the converter has a lower input current total harmonic distortion, a higher input power factor, and a higher efficiency in comparison to a conventional single-phase Z-source ac-ac converter. In addition, the experimental results show that the use of the safe-commutation strategy is a significant improvement, as it makes it possible to avoid voltage spikes on the switches. [ABSTRACT FROM AUTHOR]

Flyback topology has been widely used in low-power applications due to its simplicity, wide input voltage range, low cost, and low standby power. However, conventional over current protection (OCP) control scheme in flyback converters cannot meet the high precision constant current (CC) requirement in battery charger and LED applications. The proposed adaptive high-precision OCP control scheme can be widely used in ac/dc flyback converters to improve their CC accuracy. It consists of an OCP-Comp circuit and a Vpump circuit to detect the primary current in current cycle and adjust it in next cycle adaptively. The proposed OCP control scheme has been implemented in a controller IC adding no extra pin and achieves a significant improvement in output current accuracy compared to conventional OCP schemes. Test results show that the output current variation of the proposed prototype is less than ±0.6% when the input line voltage changes from 85 to 265 Vac. [ABSTRACT FROM AUTHOR]

The five-level modular neutral-point-clamped (5L-MNPC) converter is realized by connecting two three-level neutral-point-clamped modules in series. For five-level operation, each dc-bus capacitor voltage of the modular neutral-point-clamped topology should be regulated at one-fourth of the net dc-bus voltage. In this letter, a simple voltage-balancing approach based on the carrier-based modulation scheme is proposed to achieve the above objectives. The proposed approach uses the redundancy switching states along with the current direction and the instantaneous value of the dc-bus capacitor voltage to achieve the voltage balancing in the 5L-MNPC topology. The dynamic performance of the 5L-MNPC topology with the proposed voltage-balancing approach is verified experimentally. [ABSTRACT FROM AUTHOR]

This letter presents a single-phase cascaded transformer based multilevel inverter with a modified carrier-based level shift sinusoidal pulse width modulation (LS-SPWM) technique. The developed topology has two bridges with individual low frequency transformers. The bridges can generate quasi-square waveform and pulse width modulated waveform independently and energized the two transformers whose secondary terminals are cascaded to attain 19-level output voltage waveform across the load. The anticipated configuration has the least number of components to reduce the cost and enhance the reliability of the converter for medium power applications with inbuilt isolation. Furthermore, this letter presents the most common LS-SPWM technique with a new carrier to enhance the fundamental magnitude and shifts the dominant harmonics into three times of the traditional strategy for the same modulation indices. The performance of the proposed topology is validated with experimental results. [ABSTRACT FROM AUTHOR]

This study presents a versatile over current protection (OCP) control scheme, which can be widely used in discontinuous conduction mode (DCM) flyback converters. The proposed scheme can not only reduce the variation of output current caused by different line voltages, but also improve the performance of DCM converters in start-up, dynamic response, and the overload protection (OLP) process. It consists of an OCP compensation circuit and a current-pump circuit. Instead of being a constant value, the peak voltage across the sense resistor in a converter that uses the proposed circuit will oscillate with time when the converter regulates a constant output current. To verify the feasibility and performance of the proposed circuit, an IC controller that uses the proposed OCP circuit has been designed and fabricated in 0.35-μm 5-V/40-V high-voltage CMOS technology. Experimental results show that the constant output current precision of the prototype is within ±1% when the input line voltage changes from 90 to 265 Vac. In other tests including start-up, dynamic response, and the OLP process, the performance of the proposed prototype shows an improvement of 9%–19% over conventional converters. [ABSTRACT FROM PUBLISHER]

The conduction modes of the quadratic boost converter are explored in the context of high-dc-gain applications. A complete analytical description of the steady-state behavior of the converter operating in four possible inductor current discontinuous-conduction modes is presented. Boundaries between modes are determined together with the corresponding transitions. The study covers the operation of the converter using a pulse width modulator for constant switching frequency, and employing a hysteresis comparator for variable switching frequency. Both cases are analyzed for the same set of converter parameters and different constant resistive loads, while the converter is fed by a low dc voltage ranging from 20- to 30-V dc. Several simulations are used to verify the waveforms and average values predicted by the theoretical analysis. Experimental results in a 60-W prototype are in good agreement with the theoretical predictions, and efficiency measurements reveal that one of the discontinuous-conduction modes can compete with the continuous-conduction mode in high–dc-gain applications. [ABSTRACT FROM PUBLISHER]

The modular multilevel converter offers benefits for medium and high voltage power conversion due to indirect series connection of devices. The drawback is a large amount of capacitance that has to be installed in each module, often prohibiting its use in cost sensitive applications. This letter proposes a new operation mode of modular multilevel topologies that allows reducing the capacitance by at least an order of magnitude. To achieve this, the multilevel operation is sacrificed, but many advantages of indirect series connection, such as proper voltage sharing, small voltage steps, limited voltage slopes, modularity, and scalability remain. [ABSTRACT FROM AUTHOR]

Arm voltage and submodule (SM) capacitor voltage balancing is a key factor for the safe and reliable operation of modular multilevel converters (MMCs). The arm voltage balancing is achieved through a zero-sequence voltage controller in carrier pulse-width modulation (CPWM). In this study, a dual space-vector pulse-width modulation (SVPWM) technique is proposed for an MMC, which eliminates the external controller for arm voltage balancing. In this approach, the three-phase top and bottom arms are independently controlled using SVPWM. In addition, the capacitor voltage balancing can be achieved using redundant switching vectors. However, this will increase the computational load on the space-vector modulator. Therefore, an external capacitor voltage-balancing approach is proposed to minimize the computational complexity. The proposed approach uses the direction of load current instead of the arm current in SM selection process. As such, the required number of current sensors is reduced to 50% in a three-phase system. The proposed modulation and voltage-balancing approach are simulated and experimentally verified on the MMC system with three-level flying capacitor (3L-FC) SMs. Simulation and experimental results show the successful balancing of the arm voltage and SM capacitors voltage. [ABSTRACT FROM PUBLISHER]