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The uneven power loss distribution among the semiconductor devices is one critical issue of the three-level neutral-point clamped converter. Besides, different operating conditions will result in different loss distribution profiles. The case with low power factor and high modulation usage, which is common in the static synchronous compensator (STATCOM) application, has not been paid much attention to in the literature. In this paper, the power loss distribution under this condition is discussed. And a novel carrier-based modulation technique is proposed to balance the power loss distribution and reduce the power loss in the most stressed device. In addition, an active neutral-point (NP) voltage balancing control strategy is also proposed based on the proposed modulation scheme. Simulation and laboratory results are presented to verify the performances of the proposed modulation technique in power loss redistribution and NP voltage control. Its influence on the output current harmonic performance is also evaluated. [ABSTRACT FROM AUTHOR]

Four-level hybrid-clamped inverter is a newly proposed topology that can operate under a wide voltage range without switches connected in series. However, when it is applied in medium voltage high power conversions, the flying capacitors in each phase will occupy a huge volume and a high switching frequency is required to restrain the voltage ripples. In order to overcome this drawback, a four-level active neutral-point clamped inverter is discussed in this paper, which consists of only six switches and no diodes or flying capacitors are required. In order to balance the neutral-point voltages under the full power factor and modulation index range, a capacitor voltage balance method based on carrier-overlapped pulsewidth modulation is proposed in this paper. The upper and lower dc-link capacitor voltages are balanced by zero-sequence voltage injection and the central dc-link capacitor voltage is balanced by adjusting the duty cycles of switching signals slightly. Simulation and experimental results are presented to confirm the validity of this method. [ABSTRACT FROM AUTHOR]

The benefits of employing multilevel pulsewidth-modulated (PWM) waveforms for diagnostic purposes compared to sinusoidal- and square-shaped voltages are presented in this paper. Examples on how the high voltage circuits are designed to enable these studies, as well as results, are discussed. To demonstrate the approach, it is investigated what influence the choice of PWM levels has on the partial discharge (PD) characteristics for two similar wire specimens insulated by different materials. Here, to resemble a motor winding, two different twisted pair test objects insulated by either pure polyamide-imid (PAI) material or with added conductive Cr2O3 material were exposed to voltages with ultrashort rise times. The test objects were fed from either two-, three-, five-, or seven-level inverter waveforms of similar shape as in actual applications. To compare the performances, measurements of the PD characteristics were conducted. Specifically, the total number of PDs, as well as their average maximum amplitude per cycle, was obtained together with the phase-resolved PD pattern for each case. The experimental results presented in this paper show that the total peak and summed PD magnitude (exposure) drop considerably more for the Cr2O3 insulation compared to PAI when applying a five-level or higher level inverter. This reduction is more significant for the insulation with added Cr2O3 material and the usage of higher inverter levels reveals this. As more information can be obtained using higher inverter levels, the evaluation of new material constitutions is preferably done utilizing at least a three-level inverter or higher. [ABSTRACT FROM AUTHOR]

High-speed electrical drives normally require converters capable of high-frequency operation. For this reason, converters based on SiC mosfets have been spreading in this field. Nevertheless, the problems caused by the high dv/dt imposed by SiC mosfets, like the premature failure of the motor winding insulation and the electromagnetic interference generation, are drawing more and more attention of the experts of this sector. In fact, these issues can deeply affect the system reliability and, hence, can represent a limiting factor for all those applications where the continuity of operation is the highest priority. To avoid the use of SiC mosfets in the most sensitive applications, this paper presents a solution, which consists of a Si-insulated gate bipolar transistor (IGBT)-based inverter fed by a Si-IGBT-based dc/dc converter performing a suitable dc voltage regulation. Therefore, the aim of this paper is to prove that a stable operation of a high-speed drive can be guaranteed through the proposed converter configuration. To prove the effectiveness of the proposed solution, experimental results on a laboratory setup have been presented. [ABSTRACT FROM AUTHOR]

Cascaded H-bridge converter (CHB) is a multilevel topology that is a well-suited solution for multiple applications such as flexible ac transmission systems or motor drives. This paper is focused on a CHB where the cells present an aging mismatch. This can be caused by the maintenance operation which forces the replacement of some damaged cells of the converter with new or repaired ones. In this paper, a new improved approach of the active thermal control (ATC) of the CHB using discontinuous pulsewidth modulation (PWM) (D-PWM) is presented. The D-PWM technique is used to reduce the power losses of one cell reducing its average temperature in order to increase its remaining lifetime. However, the combination of D-PWM with traditional phase-shifted PWM (PS-PWM) introduces high harmonic distortion in the output voltage of the CHB converter at twice the carrier frequency. A detailed harmonic distortion analysis of the CHB output voltage when the D-PWM based ATC is active is presented. From this analysis, a modification of the traditional PS-PWM is derived to eliminate the harmonic distortion at twice the carrier frequency. Experimental results show how the ATC using D-PWM is achieved whereas the harmonic distortion around twice the carrier frequency is eliminated. [ABSTRACT FROM AUTHOR]

A drive train system (DTS) powered by an ideal voltage source and driving a permanent-magnet synchronous motor (PMSM) is discussed in this paper. A two-level three-phase voltage source inverter is used as a means of power conditioning. This converter is not equipped with any harmonic filters on neither the ac nor the dc side. The mechanical part of the DTS is modeled as a double oscillator according to a drive train in an electric vehicle (EV). Various inverter modulation schemes are applied, namely, a single-phase hysteresis scheme, two-space vector-based hysteresis control schemes, for one, a stator aligned hysteresis and for another, a rotor aligned hysteresis, a modulation scheme based on pulsewidth modulation (PWM), such as sinusoidal modulation (including zero-sequence components) and space-vector pulsewidth modulation (SVPWM). The hysteresis-based pulsing methods are nondeterministic and build a current controller in their structure by nature. The other pulsing methods are deterministic due to their underlying PWM and require a separate control unit. The influence of these modulation schemes on the performance of the DTS is determined by assessing the level of inverter generated harmonics flowing to the PMSM and to the tires [downforce, (mechanical part)] as well as the resulting switching frequency (electrical part). The simulated results presented in the paper indicate that the pulsing frequency can be reduced by means of the hysteresis controller. In addition, the dispersion of the harmonic energy of the inverter generated spectrum partly compensate the absence of filters. [ABSTRACT FROM PUBLISHER]

This paper investigates a method to increase fuel economy of motors for an electric vehicle (EV) traction system. The low-torque region of an EV motor is frequently used in everyday urban driving and in fuel economy measurement. Pulsewidth modulation (PWM) carrier harmonic iron loss accounts for a high percentage of total loss for EV motors in this region. This paper reveals the relationship between phase current and carrier harmonic iron loss for a permanent-magnet synchronous motor (PMSM) in the low-torque region. Thus, a novel carrier harmonic loss reduction technique is proposed and applied to two sets of three-phase windings for a concentrated winding PMSM. The loss is successfully reduced in a 70-kW EV motor as well as a two-dimensional finite-element method (2-D-FEM) calculation. The efficiency of the developed motor is calculated and compared with that of a conventional motor in the JC08 mode driving cycle. [ABSTRACT FROM PUBLISHER]

This paper proposes a two-degree-of-freedom (2DoF) interleaving scheme based on phase-disposition (PD) PWM for minimizing the high-frequency zero-sequence circulating current (ZSCC) in modular interleaved three-level converters. The method incorporates an internal interleaving by phase-shifting the carriers in each individual converter, and an external interleaving by phase-shifting the carriers of the different converters. A general harmonic distribution analysis which is valid for all types of voltage source converters is carried out to simplify the evaluation of the proposed method. A comprehensive evaluation of the proposed method shows that the PD-2DoF interleaving scheme produces the lowest ZSCC maximum value as compared to existing approaches. Moreover, it can achieve comparable performances as existing methods do in terms of output quality and common mode voltage magnitude, showing a great potential for practical implementation. Simulation and experimental results are obtained to demonstrate the performance of the proposed method. Generalization of the 2DoF interleaving scheme to high-level converter is also discussed in this paper. [ABSTRACT FROM AUTHOR]

Real-time frequency agility is one of the key limitations of current all-digital transmitters (ADTs). In this paper, to address this problem, an ADT based on direct-RF generation is proposed and implemented in a field-programmable gate array (FPGA). To achieve this, the pulse encoding is performed after the digital upconversion, which presents challenges in the pulse encoder implementation. However, the proposed design considerably improves the frequency agility when compared with current state-of-the-art approaches. Two different pulse encoders were designed in this paper, one is based on pulsewidth modulation (PWM) and the other on delta–sigma modulation ( \mathrm \Delta \Sigma \textM ). These units are implemented with high parallelization to achieve the required equivalent sampling rates. The proposed design enables the implementation of all-digital RF transmitters in FPGA with a widely tunable carrier frequency. In this paper, a variation from 0.1 up to 6 GHz of carrier frequency, with a maximum frequency resolution of 1.5625 MHz, is demonstrated. Measurement results in terms of signal-to-noise ratio (SNR) and error-vector magnitude are presented and discussed. In the case of the PWM, maximum SNRs of 39 and 36 dB were obtained for a 5 and 10 MBd of symbol rates (SRs). In the case of \mathrm \Delta \Sigma \textM , maximum SNRs of 38 and 35 dB were obtained for 20 and 40 MBd of the SR. [ABSTRACT FROM PUBLISHER]

This paper presents a new all-digital transceiver architecture fully integrated into a single field-programmable gate array chip. Both the radio frequency (RF) receiver and the transmitter were entirely implemented using a digital datapath from the baseband up to the RF stage without the use of conventional analog-to-digital converter, digital-to-analog converter, or analog mixer. The transmitter chain uses delta-sigma modulation and digital upconversion to produce a two-level RF output signal. The receiver uses a high-speed comparator and pulsewidth modulation to convert the RF signal into a single-bit data stream, which is digitally filtered and then downconverted. Both the transmitter and the receiver are agile with flexible carrier frequency, bandwidth, and modulation capabilities. The transceiver error vector magnitude and the signal-to-noise ratio figures of merit were analyzed in a point-to-point transmission to evaluate the transmitter’s performance. The results show the feasibility of this approach as a more flexible alternative to common radio architectures. [ABSTRACT FROM PUBLISHER]

In this paper, an enhanced fault-tolerant operation approach is developed to maintain continued operation of five-phase grid-tied current-source converters (CSCs) during one-phase supplying wire broken. First, the instantaneous power flow of this system is analyzed based on the sequence decomposition method. It is found that through proper arrangement of positive-, negative-, and pseudozero-sequence components of line current reference and compensation of filter CL current offset, the CSC system can achieve reduction of instantaneous active power fluctuation and minimization of line current magnitude at the same time. Accordingly, multiphase CSCs are able to operate with smaller dc rail current ripples and to obtain more active power transfer capability during fault tolerant operation. In addition, this paper also briefly discusses the control of multiphase systems in the case of complex grid faults with simultaneous wire broken and imbalanced grid voltage dips. It is found that an intentional constant reactive power injection can help to reduce the peak current of the five-phase grid-tied system. Furthermore, it should be noted that the proposed method is realized in a direct current modulation manner. Thus, a large number of line current acquisition devices for conventional multiphase grid-tied converters are removed. Finally, this paper also discusses the modulation method of five-phase CSC with one-phase wire broken. A modified “ampere-second balance” principle is applied to direct obtain the gating signals that can satisfy the constraints of CSCs. [ABSTRACT FROM AUTHOR]

Motors and inverters are increasingly being used in vehicles. As more vehicle components are being adopted, requirement for safety and installation space are increasing. Growing attention is being paid to the use of six-phase permanent magnet synchronous motors (PMSMs) and their parallel control by two inverters, because of their reduced size and enhanced safety. This paper proposes a pulsewidth modulation (PWM) control algorithm for a six-phase PMSM. In low-voltage vehicle components such as electric power steering, the current is usually acquired with resistors placed under the low-side switching devices. In the proposed control algorithm, the neutral voltage of the two inverters is shifted to either a lower or higher voltage within a certain range to allow for the signal conditioning time delay after the switching device turns on or off, and the time taken for the phase current to rise or settle. The paper proposes a novel PWM control algorithm that ensures that the on-time of the low-side switching devices satisfies the restriction on current sensing with resistors and reduces the current in the capacitor at the same time. The work contributes to reducing the current in a practical configuration involving low-voltage vehicle components. [ABSTRACT FROM AUTHOR]

This paper presents two capacitor voltage balancing (CVB) strategies for modular multilevel converter (MMC) applications. Both balancing schemes are based on model predictive control and are designed to efficiently solve a constrained optimal control problem, where the predicted capacitor voltage errors are included in the cost function with the demanded output voltage of a cluster being forced through an equality constraint. The first method proposed in this paper computes specific modulation indexes for each module using the explicit solution of a relaxed version of the original optimization problem. The second approach proposed in this paper reduces the complexity of the original problem by linearizing the objective function and using an optimal sorting network based on a greedy algorithm to solve this approximation. Considering the structures of both solution approaches, they are integrated into modulation schemes based on phase-shifted and level-shifted pulsewidth modulation algorithms, respectively. Experimental results obtained from a nine-cell single-phase MMC prototype demonstrate the good performance achieved with the proposed methodologies, as well as the implementation simplicity offered by the proposed CVB algorithms. [ABSTRACT FROM AUTHOR]

This paper presents a novel single-stage soft-switched high-frequency-link three-phase dc–ac converter topology. The topology supports unidirectional dc to ac power flow and is targeted for applications like grid integration of photovoltaic sources, fuel cell, etc. The high frequency magnetic isolation results in reduction of system volume, weight, and cost. Sine-wave pulsewidth modulation is implemented in dc-side converter. Though high-frequency switched, dc-side converter is soft switched for most part of the line cycle. The ac-side converter active switches are line frequency switched incurring negligible switching loss. The line frequency switching of ac-side converter facilitates use of high voltage blocking inherently slow semiconductor devices to generate high voltage ac output. In addition, a cascaded multilevel structure is presented in this paper for direct medium-voltage ac grid integration. A detailed circuit analysis considering nonidealities like transformer leakage and switch capacitances, is presented in this paper. A 6-kW three-phase laboratory prototype is built. The presented simulation and experimental results verify the operation of the proposed topologies. [ABSTRACT FROM AUTHOR]

Induction motor drives operated with a low ratio of the switching frequency to the fundamental frequency (i.e., pulse number) are prone to have high magnitudes of low-order torque harmonics. This paper proposes a method to analytically evaluate the harmonic torque spectrum based on the pulsewidth-modulated voltage waveforms for low pulse number operation. The predicted torque harmonic spectra for different pulsewidth-modulated waveforms are validated through simulations and experiments. This paper also reports optimal switching angles to minimize the total rms value of torque harmonics of order 6, 12, 18 $,\dots,$ $6(N-1)$ , considering the number of switching angles per quarter ($N$) to be 4 and 5. Compared to sine triangle pulsewidth modulation and selective harmonic elimination pulsewidth modulation with the same pulse number, the proposed optimal switching angles significantly reduce the total rms value of all harmonic torques of order lower than $6N$. Extensive simulation and experimental results on a 3.7-kW induction motor drive are presented to demonstrate the superior performance of the proposed optimal pulsewidth modulation. [ABSTRACT FROM AUTHOR]

This paper presents a system that enables the passive reduction of noise and vibrations in a three-phase induction machine with a stator damper winding connected to capacitors. This is a simple and effective system for reducing the flux density harmonics in an electrical machine. The theoretical study is based on the modeling of a machine equipped with the damper winding obtained from Kron's theory about equivalent circuits of electrical machinery. The analysis of the equivalent circuit allows one to identify possibilities to reduce the flux density harmonics responsible of unwanted noise and vibration components. Finally, an experimental validation is performed. [ABSTRACT FROM AUTHOR]

A dual two-level voltage source inverter (VSI) can synthesize a three-level voltage space vector employing an open-end winding induction motor. Space-vector-based pulsewidth modulation (PWM) variants for this dual VSI are proposed in this paper that offer the dual advantage of limiting the switching power loss to a single VSI at all instants and also reducing the switching commutations in the dual VSI by 50%. The influence of different error volt seconds (affected with different PWM variants) on the motor phase current in the dual VSI is critically analyzed. To this end, two analytical approaches (one using error-voltage trajectory information and the other using switching state information of the dual VSI) are also proposed in this paper to predict the current trajectory and the ripple content in the drive system. Expressions for rms ripple current are developed with different PWM variants. The efficacy of the proposed analytical approaches to predict the current trajectory and the ripple content is confirmed from the experimental results. All the PWM variants are first simulated using MATLAB and verified experimentally by conducting tests on a three-phase open-end winding induction motor drive controlled with volts per hertz control. The implementation of the PWM algorithms only requires instantaneous magnitudes of three-phase reference voltages and completely avoids the sector identification and lookup tables. [ABSTRACT FROM PUBLISHER]

This paper presents a smart image sensor with multiple operation modes, including edge extraction, multipoint tracking (MPT), and high-dynamic-range (HDR) imaging for wireless sensor nodes in Internet-of-Things applications. The pixel consists of a 0.5 V operated pulsewidth-modulation sensor for achieving HDR response and low fixed pattern noise. Array-level image signal processing is implemented using a local interpixel feedback network, in-pixel low power dynamic logics, and a corresponding peripheral with an event-driven hand-shaking readout. A prototype chip with a $64 \times 64$ CMOS image sensor (CIS) array is designed and fabricated in a TSMC 0.18- \mu \text{m} CIS technology. In the MPT mode, the measured tracking speed is 14.28 kframes/s with an error of 0.36 pixels and a tracking capability up to four points. In the HDR imaging mode, the achieved DR is 96.7 dB. [ABSTRACT FROM PUBLISHER]

This paper presents a novel multilevel radio frequency (RF) pulsewidth modulation (PWM) method for all-digital transmitters (ADTx) that actively eliminates the selected harmonics of RF-PWM. Compared with existing multilevel RF-PWM techniques, this method uses several adaptive thresholds and controls the pulsewidth of the corresponding subpulses to make the selected harmonics cancel each other out and keep the fundamental frequency component proportional to input envelope. For the third-harmonic elimination, the corresponding five-level RF-PWM scheme presented in this paper shows that it can significantly relax the filtering requirements and improve the wideband performance of the ADTx. The proposed scheme is verified by extensive simulations and offline measurements. The simulations show good potential for high-frequency operation up to gigahertz ADTx. The measured results show that the third-harmonic suppression of the proposed scheme has increased with the decreasing of the time resolution for digital implementations. For a 3.80-dB peak-to-average power ratio (PAPR) QPSK signal and a 6.04-dB PAPR 16QAM signal at 200-MHz carrier, the proposed scheme can achieve above −51- and −48-dBc third-harmonic suppression, respectively, when the time resolution is 50 ps and relative time resolution is 1%, and improves above 30 dBc to the existing schemes. [ABSTRACT FROM AUTHOR]

The pulsewidth modulation (PWM) technique is commonly used to supply modern high-speed electrical machines. The fundamental frequency is typically in the kilohertz range, with switching frequencies of several tens of kilohertz, as determined by the new SiC- or GaAs-based power transistors modules. Switching introduces minor loops in the major hysteresis cycle, with durations of the order of 100~\mu \texts or lower, with the resulting magnetization dynamics influenced by strong skin effect. However, since these minor loops have relatively small amplitude, their constitutive equation may be described by an equivalent permeability (real or complex), depending on the mean slope of the minor loop and its static energy loss. By retrieving this permeability, the classical loss is straightforwardly calculated by analytical solution of Maxwell's equations. In this paper, we measure and calculate, according to the quasi-linear approximation for the minor loops, the magnetic energy losses of 0.194 mm thick non-oriented Fe–Si 3.2% sheets subjected to PWM induction waveform. Minor loop peak amplitudes ranging between 50 mT and 0.2 T and frequencies up to 10 kHz are investigated. The results are consistent with the proposed model, to within 5%. [ABSTRACT FROM AUTHOR]

In the topology of double-inverter fed wound rotor induction machine (DI-WRIM) two voltage source inverters (VSIs) are connected one each on stator and rotor terminals. This leads to ripple in both stator and rotor currents. In this paper, these current ripples are analyzed in terms of the stator- and rotor-flux ripples, which are estimated from their respective terminals. To reduce the current ripples, the VSIs of the stator and rotor terminals are modulated with different pulsewidth modulation (PWM) sequences. The switching loss in the DI-WRIM is also analyzed for the proposed stator–rotor PWM sequence combinations, based on the flexibility of changing the power factor, by changing the flux component of the current fed from either side of a DI-WRIM drive. The proposed PWM combinations with the proposed flux component in currents are found to reduce the stator and rotor current ripples and, the switching losses. The analytically estimated root mean square current ripples for the proposed PWM combinations are validated using the simulation and the experimental results obtained from a 3-kW DI-WRIM drive. The analysis on switching losses is validated by measuring the temperature rise of heat sinks present in the individual stator and rotor side VSIs of the DI-WRIM drive. [ABSTRACT FROM AUTHOR]

With the superiority in leakage current suppression, the active voltage clamping highly efficient and reliable inverter concept (AVC-HERIC) has become a promising candidate in low- and medium-power photovoltaic systems. In addition, the high power density and low system costs have been attained in the AVC-HERIC due to the removal of the isolation transformers. However, to maintain high efficiency and good power quality under reactive power injection, prior-art modulation methods for the AVC-HERIC should be modified. In this paper, a simple modulation scheme is proposed for the AVC-HERIC, which ensures bidirectional current flow at any time. An improved modulation scheme is implemented according to the reference voltage polarity, and it is integrated into the proposed scheme to enable flexible reactive power injection. Moreover, the improved modulation scheme can maintain the same high efficiency as adopting the unipolar pulsewidth modulation strategy. More importantly, the deadtime and minimum pulsewidth limitation distortions are compensated effectively by the proposed modulation, leading to a good power quality. Simulations and experimental tests are performed on a 3-kW AVC-HERIC, and the results verify the effectiveness of the proposed modulation. [ABSTRACT FROM AUTHOR]

With the conventional secondary phase-shifted (PS) control, a semidual-active-bridge (S-DAB) dc–dc converter suffers from low efficiency at light load in buck mode due to hard switching and high tank current. In order to avoid this phenomenon and extend soft-switching range, a hybrid control including the primary pulsewidth modulation plus secondary phase-shifted (PWM+PS) is proposed in this paper. Under the proposed hybrid control, all steady-state operation modes with distinctive features are identified and analyzed. Based on the operation range, power characteristics and switching behaviors in each mode, a minimum peak current control route is developed, which can enable the converter to work with low tank current and soft switching over the whole load range. A lab-scale S-DAB converter is implemented to validate the theoretical analysis, and experimental results reveal that the higher efficiency can be achieved using the proposed control route. [ABSTRACT FROM AUTHOR]

This paper presents a 5-level inverter topology for open-end induction motor drives by using a single dc source. The open stator windings of the drive are supplied with a 3-level flying capacitor inverter from one end and capacitor-fed 2-level inverter from another end. The voltage ratio of the dc link to the capacitor in 2-level inverter is maintained at 4:1 ratio to generate five-level voltage output. The capacitor in 2-level inverter is balanced by the switching redundant vector combinations from both the inverters while the floating capacitors in the 3-level inverter are balanced by using redundant switching states. The proposed topology gives 5-level operation with less number of floating capacitors and power semiconductor switches compared to other existing topologies. Also, the balancing of the capacitors is independent of load power factor and modulation index. Further, the generalization of the proposed dual inverter scheme for any n-level inverter is also included in this paper. The experimental results and required analysis are also presented to validate the inverter scheme. [ABSTRACT FROM AUTHOR]

In this paper, a novel filter structure to suppress circulating currents is proposed based on the sequence of pulsewidth modulation voltage harmonics for high-power interleaved motor-drive systems. The sideband harmonics can be divided into positive-, negative-, and zero-sequence components. Through 120° interleaving among three paralleled inverters, a majority of positive- and negative-sequence harmonics are phase shifted. By these phase shifts, the differential-mode circulating currents between the paralleled ac–dc converters can be suppressed with the proposed filters, which have an identical structure to the three-phase common-mode chokes. Such a structure highly benefits the design and manufacturability for high-power applications where a choice of magnetic-core shapes is limited. Compared to coupled inductors (CIs) with cyclic-cascade or monolithic configurations, the number of magnetic cores can be reduced by one-third. Peak flux-linkages of the proposed filters and the conventional CIs were compared to estimate the size reduction in case of flux-limited designs. Considering the whole modulation index range, which may be required in the motor-drive systems, the maximum flux-linkage can be reduced by 50%. Prototype filters are built and showed a 33% reduction in weight and size compared to the conventional CIs. The validity of the proposed filter is verified through the simulation and a small-scale experiment. [ABSTRACT FROM AUTHOR]

It is well known that spatial field harmonics will cause high eddy current losses in surface-mounted permanent magnets (PMs) especially for the fractional-slot PM motors. However, the influence of temporal current harmonics, especially of the high-order temporal harmonics caused by pulsewidth modulation voltages from an inverter, lacks attentions. This paper studies the eddy current losses of the PMs caused by high-order current harmonics. In order to simplify the calculation and save computation time, analytical methods are used to predict the current harmonics caused by the PWM inverter, and the armature reaction field, the eddy current density, and losses in the PMs generated by the current harmonics. Finite element analysis, coupling simulation, and experimental studies are used to verify the analytical results. The study results show that the high-order current harmonics cause much higher eddy current losses than those caused by slotting and fundamental current even though the amplitudes of the high-order current harmonics are much lower. [ABSTRACT FROM AUTHOR]

Parallel interleaved two-level (2L) three-phase voltage source inverters (VSIs) are widely used due to their distinct advantages of high power delivery, modularity, low current rating devices, etc. Along with these advantages, the parallel interleaved 2L VSIs could also be analyzed as a single three-level (3L) VSI. Conventionally parallel interleaved 2L VSIs are modulated using the 2L pulsewidth modulation (PWM) techniques. However, implementation of parallel interleaved 2L VSIs using the 2L PWM techniques may generate a higher ac side current ripple as compared to implementing the parallel interleaved 2L VSIs using 3L PWM techniques. This paper proposes a carrier-based method for implementing different 3L discontinuous PWM (DPWM) techniques for parallel interleaved 2L three-phase VSIs. Comparison of different 2L switching sequences for implementing a 3L DPWM switching sequence based on circulating current, line current ripple, and switching loss is also carried out. Simulation and experimental results are also displayed to validate the proposal. [ABSTRACT FROM AUTHOR]

This paper presents the design, characterization, and testing of an ultrasonic transducer driver capable of arbitrary waveform generation with a bandwidth of up to 1 MHz and an output range of ±96 V. The architecture is derived from bridged class-D switching amplifiers and has a five-level power stage. The proposed device was implemented with eight synchronized channels and an all-digital control circuitry to transmit guided-wave ultrasound signals using custom piezoelectric multi-element array transducers, allowing programmable mode selectivity. [ABSTRACT FROM AUTHOR]

Power line communication (PLC) technology has proved itself in the last decade as an interesting solution for data transmission and communication in domestic application. Lately, this technology has been considered as a potential solution for monitoring and diagnosis of a motor-fed inverter setup. Information issued from sensors would be sent via power cables back to the controller despite the harsh environment and the switching of the inverter. This paper discusses the use of PLC technology over a pulsewidth modulation network by underlining the effect of the power cable length and the inverter switching on communication. A new approach based on the measurement of scattering parameters is used for this purpose, and the effect of the cable length is analyzed. It is shown that, for long distances, the PLC technology may not be effective, and hence, it is not possible to use power cables for communication. [ABSTRACT FROM PUBLISHER]

For variable-speed drives, the interaction of the machine and the converter is becoming increasingly important, especially for high-speed applications, mainly due to the effect of the converter modulation on the machine losses. The allocation of the losses to different components of the drive system needs to be known in order to choose the ideal machine and modulation combination. In this paper, individual models are introduced for calculating the rotor, copper, and core losses of the machine as well as the inverter losses, taking the modulation type into account. These models are developed by considering two typical high-speed permanent-magnet synchronous motor topologies (slotted and slotless machines) driven by pulse-amplitude modulation (PAM) and pulsewidth modulation (PWM) converters. The models are applied to two off-the-shelf machines and a converter operating with either PAM or PWM. The test bench used to experimentally verify the models is also described, and the model results are compared to the measurements. The results show that PAM produces a higher overall efficiency for the high-speed machines considered in this paper. However, PWM can be used to move the losses from the rotor to the converter at the expense of decreasing the overall drive efficiency. The possible benefits of these results are discussed. [ABSTRACT FROM PUBLISHER]

The Z-source inverter (ZSI) employs an LC impedance network between the main inverter bridge and the power source. The unique feature of the ZSI is that it can operate either in buck or boost mode with a wide range of obtainable output voltages from a given input voltage. This topology also exhibits better electromagnetic-interference noise immunity when compared to a traditional voltage-source inverter (VSI). However, the LC impedance network of ZSI significantly increases the size and cost of the power converter and can make it unsuitable for low-power applications. This paper proposes a novel topology called switched boost inverter (SBI) which exhibits similar advantages of ZSI with lower number of passive components and more active components compared to ZSI. The steady-state and small-signal analyses of SBI, along with its pulsewidth modulation (PWM) control strategies, have been discussed in this paper. This paper also presents a comparison of SBI and ZSI with the same input and output parameters. The theoretical analysis given in this paper has been validated using a laboratory prototype of SBI, and the experimental results are presented for verification. The experimental harmonic spectrum of the inverter's output voltage with the proposed PWM technique is also plotted and compared with that of a traditional VSI. All the experimental results show good correlation between theory and experiments. [ABSTRACT FROM PUBLISHER]

Part I of this paper has proposed a duty-cycle-space-vector (DCSV)-based modulation strategy for three- and four-leg matrix converters (MCs). This paper develops a digital DCSV-based modulation strategy for the three- and four-leg MCs based on the results of Part I of this paper. The digital DCSV-based modulation strategy is implemented in a DSP–field programmable gate array (FPGA) platform. The objective is to reduce the calculation time of the modulation algorithm by performing the following: 1) reducing the total number of instructions needed to implement the modulation algorithm in the DSP and 2) implementing parts of the modulation algorithm in an FPGA to generate the switching pattern. Therefore, the calculation process of the modulation algorithm is split between the DSP and the FPGA. [ABSTRACT FROM PUBLISHER]

Applying pulsewidth modulation (PWM) to control the gain in audio codecs for mobile applications leads to several advantages, such as the smooth control of tuning parameters, smaller silicon area, and lower power consumption, as compared with other tuning techniques using programmable gain amplifiers and zero crossing detectors. The PWM has to be embedded into the main signal path, preferably in a closed-loop control scheme, in order to exploit its benefits. However, the insertion of dithering and offset controls in a gain setting loop poses the problem of controlling their effects in all gain conditions. This paper reports a novel technique aimed at solving the associated issues and limitations, and provides the experimental proof of the concept through the implementation of a test-chip design on silicon. In particular, this paper reports the design and experimental results of a delta–sigma analog-to-digital converter featuring a click-free gain control technique, dithering insertion, and idle-tone shifting, which has been implemented in a 40-nm complementary metal–oxide–semiconductor technology for commercial telecom audio codec applications. [ABSTRACT FROM PUBLISHER]

This paper explores the issue of the neutral-point oscillation in the four-leg neutral-point clamped inverter. Such an issue is closely associated with the neutral-point current, so this study models the inverter on the dc side to clarify its relationship and presents a three-dimension pulsewidth modulation to eliminate the neutral-point oscillation. In addition, an offset-injection approach to reducing the neutral-point oscillation is also investigated and discussed. The laboratory test results will validate the analysis of the proposed approach, and a discussion will be presented to evaluate the effectiveness of eliminating the neutral-point oscillation. [ABSTRACT FROM AUTHOR]

This paper focuses on a minimal current sensing strategy and fault detection of switched reluctance machines (SRMs). In order to reduce the number of required current sensors in multiphase motor drives, the optimal selection and location of current sensors is presented in consideration of the precise actual phase current measurement, open- and short-circuit fault detection. The proposed scheme requires two current sensors to replace the phase current sensors placed in each phase without any additional devices for multiphase SRMs to achieve a more compact and low-cost drive. Different current regulation methods are employed for single phase conducting region and commutation region. To obtain the phase currents from the proposed approach, different settings of the pulsewidth modulation signals for adjacent phases during the commutation region are implemented. The simulation and experiments on a four-phase 8/6 pole SRM are carried out to verify the effectiveness of this approach in the healthy and faulty cases. [ABSTRACT FROM AUTHOR]

Among multilevel converter topologies, the cascaded H-bridge (CHB) converter is one suitable solution for multiple applications, such as flexible ac transmission systems and motor drives. CHB presents a natural high modularity because it is formed by the serial connection of H-bridges. This paper deals with a CHB where the cells do not have the same aging because the maintenance during the years of operation forces to replace some damaged cells of the converter with new or repaired ones. A method based on clamping one power cell can be used to reduce the power losses of that cell reducing its temperature and increasing its lifetime. However, clamping one cell of the CHB introduces high harmonic distortion around twice the carrier frequency due to the CHB unbalanced operation when a conventional phase-shifted pulsewidth modulation (PWM) is applied. A deep harmonic distortion analysis of the CHB output voltage with thermal control based on clamping one cell is presented. Using this analysis, the harmonic distortion at twice the carrier frequency is eliminated applying a nonconventional phase-shifted PWM where the angles between the carriers of consecutive power cells are modified. Experimental results show how the thermal control applying the clamping of a power cell is achieved while the harmonic distortion around twice the carrier frequency is eliminated. [ABSTRACT FROM AUTHOR]

Core loss estimation of filter inductors is increasingly important for modeling and optimizing high-frequency, high-efficiency, and high-density pulsewidth modulation (PWM) power electronic converters. However, data provided by inductor core manufacturers are insufficient for core loss estimation in PWM converters, particularly in the case of customized gapped inductors. This paper presents a whole process of characterizing and estimating the core loss of a customized high-current gapped inductor for PWM converters. To excite the inductor for the B–H loop measurement, a test circuit formed by a half-bridge structure is proposed, which has the ability to compensate the asymmetric rectangular voltage on the inductor caused by the device voltage drops. To overcome the other challenges raised by a high excitation current, a refined discontinuous test procedure, triple pulse test, is proposed to reduce the requirements of the high-current test setup (thermal stress, current–time stress for current probes, capacity of dc sources, etc.). For practical purposes, a user-friendly loss map approach is proposed involving only time-domain and electrical variables to replace magnetic variables to enable the straightforward loss mapping process and core loss calculations. Presented experimental results show consistency between the estimated inductor loss and measured values. Overall, the proposed testing approach can be easily implemented on the user's side to develop a loss map of a given inductor. The established core loss map enables the users to accurately and rapidly estimate the core loss of a tested inductor for given PWM waveforms. [ABSTRACT FROM AUTHOR]

Two parallel interleaved two-level (2L) three-phase voltage source inverters (VSIs) can be analyzed as a single three-level (3L) VSI. A generalized carrier-based method is proposed in this paper for implementing different 3L pulsewidth modulation (PWM) techniques using two parallel interleaved 2L VSIs. The proposed method modifies the given three-phase reference signals of 3L VSI for implementation of the PWM technique using two parallel interleaved 2L VSIs. The influence of nonidealities on the equivalent 3L PWM switching sequences is also discussed. To overcome the effect of nonidealities, a new modified discontinuous PWM technique (MDPWM1) is proposed. The analysis of different performance indices is carried out for different 3L PWM techniques, and the key advantages of different PWM techniques are identified. Simulation and experimental results are also presented. [ABSTRACT FROM AUTHOR]

Standard pulsewidth modulation (PWM) schemes for modular multilevel converters (MMC) have neglected deviations of the module voltages from the mean module voltage of an MMC arm as well as the dynamic change in the module voltages since their last measurement and during the switching period. This induces an output voltage error. Large output voltage errors disturb the higher level closed-loop control of the MMC, such that control targets cannot be met anymore. The output voltage error can be reduced using advanced PWM methods that predict and include the dynamic change of the individual module voltages during a switching period in the calculations for the duty cycle. This paper shows measurement results obtained from an experimental medium-voltage prototype, proving that advanced methods lead to much lower output voltage errors than the standard methods, but cannot fulfill the expectations raised by the simulations documented in the literature. In order to overcome the limitations of the old method, a new method that includes the semiconductor voltage drop and parasitic resistances is introduced and evaluated with measurements in this paper. Furthermore, simulation results showing the influence of the considered modulation methods on the closed-loop current control performance are presented. [ABSTRACT FROM AUTHOR]

A fully digital driving circuit for thin-film transistor liquid crystal display can offer benefits, including less power consumption and a shortened design schedule. Using the pulsewidth signal to control the moment to stop the ramp voltage, the pixel voltage can be set accurately. In this paper, the possible issues of power consumption, device nonuniformity, and parasitic capacitance are well-studied to prove the feasibility and advantages of the digital driving method. It is prospectively expected to substitute for the conventional analog driving method in the future. [ABSTRACT FROM AUTHOR]

This paper proposes a general control scheme for the dual-input three-level inverter, which comes from a neutral point clamped three-level inverter. It can be used for photovoltaic (PV) systems or battery storage systems with two dc sources. The dual-input three-level inverter can be connected with two PV arrays, which are able to realize maximum power point tracking independently. First, the dynamic model of the dual-input three-level inverter is established, which describes the relationship between the dual-input voltages and the duty cycle. After discussing the control theory of the dual-input voltages, a typical control scheme is proposed. The design of a control loop is introduced in details. Afterward, modulation and restriction of the proposed method are discussed. Finally, experiment on a 125 kW dual-input three-level PV inverter is implemented to verify the validity and feasibility of the proposed method. [ABSTRACT FROM AUTHOR]

Interleaved three-phase voltage source converters (VSCs) are widely applied in industry. The circulating current issue has been the focus so far in literature. However, the common-mode voltage (CMV) generated from interleaved VSCs, which is also a key factor that influences the system's performance, has not yet been studied in detail. In this paper, the impact of pulsewidth modulation (PWM) strategies on the CMV of interleaved two-level VSCs is analyzed. The analysis is conducted based on the double Fourier integral theory and in a generalized way considering an arbitrary number of interleaved converters. Five PWM schemes are considered, including the interleaved sinusoidal PWM (ISPWM), the interleaved space vector modulation (ISVM), the interleaved discontinuous PWM (IDPWM), and the recently proposed interleaved carrier phase-shift PWM (ICPS PWM), and interleaved carrier phase-shift SVM (ICPS SVM). Both magnitude and harmonic content of CMV are examined for each method. The analysis reveals that with ISPWM, ISVM, ICPS PWM, and ICPS SVM, the CMV can be reduced. In contrast, interleaving has little impact on the CMV with IDPWM, which is always at VDC/2 due to high low-order harmonics, making it less attractive for drive applications using coupled architecture. For modular architecture, ICPS PWM and ICPS SVM are more desirable considering their low-ZSCC peak value. The study is verified through experimental results. [ABSTRACT FROM AUTHOR]

LLC resonant converter is a soft switching frequency modulated dc–dc topology with its switching frequency near the resonant frequency. However, in applications where a wide output voltage is desired, it is extremely difficult to tune its operation close to the resonant frequency. In this paper, a novel pulsewidth modulated LLC type resonant converter based on voltage quadrupler rectifier is proposed. The proposed converter always operates at the resonant frequency and is able to achieve a wide output voltage range by modulating the duty cycle of the secondary side auxiliary mosfet. This brings the benefits of the decreased circulating current and corresponding conduction loss, as well as the simplification of the parameters selection and magnetic component design. Zero-voltage-switching and zero-current-switching are realized among all power mosfets and all power diodes, respectively. Detailed circuit operation principles and modeling method are presented. A 1.3-kW converter prototype, generating 250–420 V output from 390-V dc-link is designed. Both the circuit functionality and the theoretical analysis are verified in the experimental results. [ABSTRACT FROM AUTHOR]

This paper presents a nine-level transformer-based inverter requiring only eight switches. The envisaged structure consists of two standard H-bridges fed from a single dc source. Besides, a single-phase transformer is employed to aid the process of intermediate voltage level generation. An ad-hoc pulsewidth modulation scheme based on boolean logic form equations is developed to derive the gating pulses. An effortless extension of the proposed inverter to a higher number of voltage levels is also achieved by generalizing the switching functions. Furthermore, the superior performance of the proposed topology is demonstrated through a comprehensive cost-based analysis. Finally, the validation of the proposed topology is accomplished through experiments on a down-scale prototype, and the measurement results are included. [ABSTRACT FROM AUTHOR]

This paper illustrates the application of a solving method of linear systems to a multilevel inverter. This study applies a generic pulsewidth modulation (PWM) method to a multilevel topology. This method finally highlights some specific modulation schemes. First, the study describes the mathematical model of the inverter leg. The leg is made of three level T-type structure. The model is extended to the three-phase inverter. The generalized inverse is used to generate the solution set of the conduction rates. Among the modulation strategies possible, three specific modulation schemes are proposed. The modulation schemes are applied to simulate a PWM three-phase inverter. Finally, some experimental results complete the analysis. [ABSTRACT FROM AUTHOR]

Multilevel inverters have been widely used in medium- and high-voltage applications. Selective harmonic elimination for the staircase voltage waveform generated by multilevel inverters has been studied extensively in the last decade. Most of the published methods on this topic were based on solving high-order multivariable polynomial equation groups derived from Fourier series expansion. This paper presents a different approach, which is based on equal area criteria and harmonic injection. With the proposed method, regardless of how many voltage levels are involved, only four simple equations are needed. The results of a case study with maximum of five switching angles show that the proposed method can be used to achieve excellent harmonic elimination performance for the modulation index range at least from 0.2 to 0.9. To demonstrate the adaptability of the proposed method for waveforms with a high number of switching angles, experimental results on a 1-MVA 6000-V 17-level cascade multilevel inverter are also shown at the end of this paper. [ABSTRACT FROM AUTHOR]

Many relevant concepts related to series connection and independent control of multiphase machines supplied from a single current-controlled voltage-source inverter (VSI) have recently been demonstrated by several researchers. These previous evaluations give great contribution to further improvements of multimachine series-connected devices and reduced count VSI applications. Following the initial proposition, which includes an evaluation based on the general theory of electrical machines, this paper evaluates pulsewidth modulation schemes for two-motor series-connected motor drives. The goal of this paper is to show how to achieve independent feedforward voltage control and to evaluate the switched voltage profile in the motors' windings and their behavior. Scalar and vector approaches are addressed, and simulation and experimental results are shown to illustrate the details discussed in this paper. [ABSTRACT FROM AUTHOR]

An indirect matrix converter is an alternative "all-semiconductor" energy processor proposed recently for converting an ac source with fixed magnitude and frequency to a variable voltage and frequency supply that can meet the requirements of a particular industry application. In principle, an indirect matrix converter is constructed by connecting a front-end bidirectional rectification stage to a conventional two-level inversion stage with no bulky capacitive or inductive energy storage connected to their intermediate dc link. Through the proper modulation and compensation of the resulting converter, sinusoidal input current and output voltage can be achieved with minimized rectification switching loss, rendering the indirect matrix converter as a competitive choice for interfacing the utility grid to, e.g., defense facilities that require a different frequency supply. As an improvement, an indirect matrix converter assembled using a three-level energy, processing stage has briefly been mentioned in the literature, but has neither been tested in simulation nor experimentally because its operational principles, pulsewidth-modulation (PWM) control, and index compensation have not yet been discussed in the existing literature. Addressing the previously described issues, this paper focuses on the operational mode analysis of a three-level indirect matrix converter implemented using a neutral-point-clamped inversion stage and the design of a number of PWM and modulation ratio compensation schemes for controlling the converter with improved waveform quality. The performances and practicalities of the designed schemes are verified in simulation and experimentally using an implemented laboratory prototype with some representative results captured and presented in this paper. [ABSTRACT FROM AUTHOR]

A five-level symmetrically defined multilevel selective harmonic elimination pulsewidth modulation (MSHE-PWM) strategy is reported in this paper. It is mathematically expressed using Fourier-based equations on a line-to-neutral basis. An equal number of switching transitions when compared against the well-known multicarrier phase-shifted sinusoidal PWM (MPS-SPWM) technique is investigated. For this paper, it is assumed that the four triangular carriers of the MPS-SPWM method have nine per unit frequency resulting in seventeen switching transitions for every quarter period. For the proposed MSHE-PWM method, this allows control of sixteen harmonics and the fundamental. It is confirmed that the proposed MSHE-PWM offers significantly higher converter bandwidth in the standard range of the modulation indices. Moreover, when the bandwidth is reduced to be equal with the one offered with the MPS-PWM, the modulation index can be increased resulting in a higher gain and at a reduced switching frequency overall. Selected solutions for the switching transitions are presented and verified experimentally in order to confirm the effectiveness of the proposed technique. [ABSTRACT FROM AUTHOR]