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The 2019 International Conference on Modeling and Analysis of Semiconductor Manufacturing (MASM 2019) was part of the 2019 Winter Simulation Conference (WSC) that was held December 8–11 in National Harbor, MD, USA. The MASM conferences provide a forum for the exchange of ideas and industrial innovations between researchers and practitioners from around the world involved in modeling and analysis of complex high-tech manufacturing systems. While the papers from MASM conferences are of high quality and are often cited in journal papers, they are limited in size. As a premier journal for topics covered in the MASM conferences, IEEE Transactions on Semiconductor Manufacturing, agreed to consider extended article submissions based on the 21 papers accepted and presented at the MASM 2019 conference for a Special Section of an upcoming issue of the journal. were sessions on Scheduling and Dispatching, Fab Scheduling, Maintenance and Engineering, Capacity and Production Planning, Qualification and Wafer-to-Order Allocation, Semiconductor Manufacturing Models, and Semiconductor Modeling Representations. Dr. Sabine Herlitschka, Chief Executive Officer and Chief Technology Officer of Infineon Technologies Austria AG, gave an excellent keynote talk titled “A European View on Future Semiconductor Industry Needs for MASM.” An archive of the MASM 2019 papers can be found at https://informs-sim.org/wsc19papers/by_area.html. [ABSTRACT FROM AUTHOR]

As this Special Section goes to publication, semiconductor manufacturing in the United Status, and globally, continues to expand at a seemingly torrid pace. Assisted by government funding and driven in part by artificial intelligence workloads that gobble up increasing amounts of data center computing capacity, Intel and TSMC fabs are going up in Arizona, TI and Samsung fabs are coming to Texas, and Micron has big plans in New York. Unfortunately, just like those flying cars we were once promised, AI has not yet eliminated the need for the skilled trades and engineers required to build and successfully operate a fab. As a result, workforce development has become an important part of the increasingly complex semiconductor manufacturing process: Where are the thousands of engineers the semiconductor industry needs to staff these new fabs going to come from? How can we make more students excited about science and engineering? While the Guest Editors don’t have all the answers, we are happy that ASMC contributes to the solution by actively supporting student presentations and posters and annually recognizing the best student paper of the conference. And, maybe some day, the artificial intelligence systems that semiconductor manufacturing has enabled will give us those Star Wars or Star Trek robots that can build fabs and make chips too. [ABSTRACT FROM AUTHOR]

The semiconductor industry is the core industry of the information age. As a key link in the semiconductor industry, wafer fabrication plays a key role in its development. In the testing stage of the wafer, each die of the wafer is detected and marked, and a wafer map with a certain spatial pattern can be formed. The analysis and classification of these spatial patterns can identify the cause of wafer defects, thereby improving production yield. However, as wafer size increases, line widths become smaller, etc., the probability of a mixed defect mode wafer pattern increases. Moreover, the mixed defect mode wafer map is more difficult to identify and classify than the single defect mode wafer map. Therefore, this paper proposes an improved deep convolutional neural network (DCNN) structure model for the recognition and classification of mixed defect pattern wafer maps. From the perspective of increasing the width of the DCNN, the improved network structure can avoid problems such as over-fitting and limited extraction of features due to the continuous deepening of the DCNN. The network is called Multi-Path DCNN (MP-DCNN) structure. The experimental results show that the proposed Multi-Path DCNN structure has better performance and higher classification accuracy than existing methods. [ABSTRACT FROM AUTHOR]

The article announces that the paper entitled "Across Wafer Critical Dimension Uniformity Enhancement Through Lithography and Etch Process Sequence: Concept, Approach, Modeling, and Experiment," by Qiaolin Zhang, Kameshwar Poolla and Costas J. Spanos received the 2007 Transactions on Semiconductor Manufacturing Best Paper Award.

The article announces that "Model-Based Design Analysis and Yield Optimization," by Tobias Pfingsten, Daniel J. L. Herrmann, and Carl Edward Rasmussen has been recognized as the best paper by the IEEE Transactions on Semiconductor Manufacturing.

The article presents information about the Best Paper Award by the journal "IEEE Transactions on Semiconductor Manufacturing." The paper entitled "Characterization of Spatial Intrafield Gate CD Variability, Its Impact on Circuit Performance, and Spatial Mask-Level Correction," by Michael Orshansky, Linda Milor and Chenming Hu has been recognized as the best paper published in the 2004 issue of the journal. This paper, which appeared in the February 2004 issue, has been chosen for its development of methods to measure and analyze spatial within-chip variations, to understand the impact that these variations have on circuit speed, and to compensate for these variations.

This paper addresses the quality control of the photolithography process in the semiconductor industry. Overlay errors in the process seriously affect the wafer yield, and cause the wafer to be forced to rework and affect the production efficiency of the equipment. We examine the current state of its process control, develop a novel overlay predict model, and verify the prediction results. This study proposes a Global Attention Generative Adversarial Networks (GAGAN) model to precisely predict the overlay error for the feed-forward data of the front layer, which is used as the important information and process parameters for the advanced process control of the current layer. Experiment results on a semiconductor shop-floor confirms that our proposed method achieves high predictive performance while maintaining extensibility and visual quality. [ABSTRACT FROM AUTHOR]

Announces that Venkat K.R. Chiluvuri and Israel Koren have been awarded the IEEE Transactions on Semiconductor Manufacturing Best Paper Award for their paper entitled `Layout Synthesis Techniques for Yield Enhancement.' Description of the award; Profiles of the awardees.

The ten papers in this special section are enhanced versions of some of the best papers from the 2012 SEMI Advanced Semiconductor Manufacturing Conference. [ABSTRACT FROM AUTHOR]

A variety of processes in the semiconductor industry require heating of the silicon wafer to the desired temperature. This process is widely referred to as rapid thermal processing. However, the contactless measurement of the surface temperature of the wafer is still a major challenge, especially in the case of rotating wafers. Measurements using infrared cameras are not suitable due to the fact that silicon is transparent in this wavelength range. Special sensors based on the principle of pyrometry are available, but such sensors can only measure the surface temperature at one single point. This paper presents an observer approach that estimates the wafer’s surface temperature by using the temperature measurement of only one pyrometer. The approach is based on a mathematical model capturing the dynamical behavior of the wafer’s temperature. It relies mainly on the quasi-linear heat equation. Real world experiments demonstrate the achieved accuracy of the proposed approach. [ABSTRACT FROM AUTHOR]

With the globalization of semiconductor industry, hardware security issues have been gaining increasing attention. Among all hardware security threats, the insertion of hardware Trojans is one of the main concerns. Meanwhile, many current Trojan detection solutions follow the assumption that the hardware Trojan itself should be composed of digital logic. This assumption is invalidated by recently proposed analog Trojans which are extremely small and can detect rare events. This paper proposes a runtime hardware Trojan detection method which is geared toward detecting such advanced Trojans. The principle of this method is to guard a set of concerned signals, and initiate a hardware interrupt request when abnormal toggling events occur in these guarded signals. To prove the effectiveness of this method, we design a processor based on ARMv7-A&R ISA, and insert an analog Trojan into the processor. We fabricated the design in an SMIC 130-nm process and demonstrate the effectiveness of the proposed methodology. [ABSTRACT FROM AUTHOR]

3-D-stacked integrated circuits (ICs) that employ through-silicon vias (TSVs) to connect multiple dies vertically have gained wide-spread interest in the semiconductor industry. In order to be commercially viable, the assembly yield for 3-D-stacked ICs must be as high as possible, requiring TSVs to be reparable. Existing techniques typically assume TSV faults to be uniformly distributed and use neighboring TSVs to repair faulty ones, if any. In practice, however, clustered TSV faults are quite common due to the fact that the TSV bonding quality depends on surface roughness and cleanness of silicon dies, rendering prior TSV redundancy solutions less effective. Furthermore, existing techniques consume a lot of redundant TSVs that are still costly in the current TSV process. This inefficient TSV redundancy can limit the amount of TSVs that is allowed to use and may even become the obstacle to commercial production. To resolve this problem, we present a novel TSV repair framework, including a hardware redundancy architecture that enables faulty TSVs to be repaired by redundant TSVs that are farther apart, the corresponding repair algorithm and the redundancy architecture construction. By doing so, the manufacturing yield for 3-D-stacked ICs can be dramatically improved, as demonstrated in our experimental results. [ABSTRACT FROM AUTHOR]

Silicon (Si) insulated-gate bipolar transistors (IGBTs) are widely used in power converters. Silicon carbide (SiC) technology will push the limits of switching devices in three directions: higher blocking voltage, higher operating temperature, and higher switching speed. The first SiC–metal–oxide–semiconductor field-effect transistor (MOSFET) half-bridge modules (SiC HBM) are now commercially available and look promising. Although they are still limited in breakdown voltage, these components should, for instance, improve traction-chain efficiencies. In particular, a significant reduction in switching losses is to be expected which should lead to improvements in power-to-weight ratios—of particular interest for rolling-stock. Nevertheless, because of the high switching speed and the high current levels required by traction applications, the implementation of these modules is critical. In this paper, the authors investigate the parallel connection of SiC HBM with a focus on traction equipment. The key points are underlined and an original approach is proposed to design the bus-bar and the gate-drive circuit. Experimental results performed on an opposition method test bench, valid the correct operation of three SiC modules in parallel. [ABSTRACT FROM AUTHOR]

Dear readers—We hope this editorial finds you and your family safe as we and the world battle—or, hopefully at the time of this publication, recover from—perhaps the greatest world-wide health crisis in the last century, COVID-19. Fortunately, the contributions of our semiconductor manufacturing industry over the last 40 years have put us in a much more comfortable position than those who faced past pandemics. It is likely that many of you have been working from home using your high-speed Internet connection and one of multiple computers that you and most families own. The worldwide Internet and computing infrastructure that our industry has enabled allows many engineers and others to VPN into work, communicate and share documents via e-mail, and attend video meetings. On the personal side, you can keep up with family and friends, with the latest news, and information and instructions from the government. Semiconductors allow your children to attend (or perhaps teach) school remotely. Certainly school aged children will be missing contact with their friends, but, fortunately, they can still video chat, message, or at least call friends with their mobile phones. The whole family can enjoy their favorite shows and movies via streaming services, and of course try new video games. [ABSTRACT FROM AUTHOR]

The semiconductor industry has become fully automated during the manufacturing process and abundant process parameters are collected online by sensors for fault detection and classification purposes. Analyzing process parameters and identifying a smaller set of key parameters that have crucial influence on wafer quality will bring great benefits in stabilizing the manufacturing process and enhancing productive yield. Typically, this type of the parameter set is called the “raw trace data.” This paper considers image processing techniques as a novel approach for analyzing and visualizing the raw trace data. First, the 1-D time series data of a wafer batch was transformed into a 2-D image. Fisher’s criterion ratios of the labeled good and defective wafer image maps are computed to identify the key parameters. The key parameters identified by the proposed image processing technique are consistent with the technical experience of the process engineers. Furthermore, the texture analysis technique with 2-D Fourier transform is utilized to analyze the images of the key parameters to detect defective wafers. The proposed key parameter identification and wafer classification method proves to be a viable solution under the paradigm of advanced process control practice for semiconductor manufacturing. [ABSTRACT FROM AUTHOR]

In this paper, a model predictive scheme is proposed to control the grid-connected high-power four-level diode-clamped inverter. To predict the future behavior of active and reactive grid power values and dc link capacitor voltages, a discrete-time model of the inverter is developed in synchronous reference frame. The controller uses all the possible switching states of the inverter for the prediction and evaluates them using a cost function. The switching state, which minimizes the cost function, is then chosen and applied at the next sampling interval. The switching frequency minimization is also achieved by including an extra constraint in the cost function. A simplified extrapolation method with reduced computational burden is proposed to safeguard the semiconductor devices during the dynamic changes in reference power values. The performance of the proposed method is investigated with the perturbations in the grid filter and dc link parameters. The feasibility of the proposed method is verified through simulation and experimental results, showing good dynamic and steady-state performance. [ABSTRACT FROM PUBLISHER]

As technology scales down, IC design is becoming more difficult due to the increase in process variations, which translates into a dispersion of circuit parameter values thus degrading manufacturing yield. Regular layouts are recommended to reduce variability with the cost of area overhead with respect to conventional layouts. The aim of this paper is to measure the impact of variability in two implementations of the same circuit in a commercial 40-nm technology: 1) a regular layout style and a compact and 2) nonregular layout. Experimental results show a 60% reduction in variability with a cost of 60% area overhead. [ABSTRACT FROM PUBLISHER]

Almost one year ago, we sent selected authors who had presented at the SEMI Advanced Semiconductor Manufacturing Conference 2015 the following letter. [ABSTRACT FROM AUTHOR]

As the feature size keeps scaling down and the circuit complexity increases rapidly, a more advanced hybrid lithography, which combines multiple patterning and electron-beam lithography (EBL), is promising to further enhance the pattern resolution. In this paper, we formulate the layout decomposition problem for this hybrid lithography as a minimum vertex deletion K -partition problem, where K is the number of masks in multiple patterning. Stitch minimization and EBL throughput are considered uniformly by adding a virtual vertex between two feature vertices for each stitch candidate during the conflict graph construction phase. For K = 2 , we propose a primal-dual (PD) method for solving the underlying minimum odd-cycle cover problem efficiently. In addition, a chain decomposition algorithm is employed for removing all “noncyclable” edges. Furthermore, we investigate two versions of the PD method, one with planarization and one without. For K > 2 , we propose a random-initialized local search method that iteratively applies the PD solver. Experimental results show that compared with a two-stage method, our proposed methods reduce the EBL usage by 65.5% with double patterning and 38.7% with triple patterning on average for the benchmarks. [ABSTRACT FROM PUBLISHER]

The semiconductor industry is facing a twofold challenge at sub-nanometer level; first, the high power dissipation in irreversible computing architectures due to information loss and second, inability to handle large data due to sequential information processing. These issues create obstacles in producing the presumed low-power complex computing outcomes. The heat dissipation can be reduced by utilizing the complementary metal–oxide–semiconductor-based reversible computing architectures. However, these architectures fail to enhance the performance owing to inability to process large data. Quantum computing (QC) can circumvent these problems due to its fundamental ineffaceable characteristics of quantum mechanics-based reversible computing and parallelism. Spin-torque-based physical realization is the most suitable platform for reversible computing due to the electron spin analogous to the qubit. However, optimal quantum circuits are required to physically realize the complex Boolean logic due to spin-qubit decoherence and reduce the number of transistor switching activities for the spin generation and injection required for the spin-qubit rotation. Therefore, in this paper, optimal quantum circuit decompositions are presented with the help of developed elementary quantum library { $R_{y}^{(\theta)}$ , $R_{z}^{(\theta)}$ , $\sqrt {\text {SWAP}}$ } for the spin-torque-based QC architecture. The reversible Boolean logic performance is analyzed and compared for the conventional, reduced, and optimal decompositions on the first- and second-order transmission coefficient matrix-based spin-torque QC architecture. The results encourage to set a path toward QC-based reconfigurable complex computing systems in near future. [ABSTRACT FROM AUTHOR]

Dielectric barrier discharge (DBD) and packed-bed reactor (PBR) are two of the commonly used nonthermal-plasma (NTP) reactors. In this paper, these two reactors are applied to remove two perfluorocompounds (PFCs), i.e., CF4 and SF6, which are extensively used in semiconductor- and liquid-crystal-display-manufacturing industries. Experimental results indicated that PBR constructed by packing dielectric pellets (chemical com- positions: CuO 64%, ZnO 24%, Al2O3 10%, and MgO 2% by weight) inside the DBD reactor achieved a higher CF4 removal efficiency and a lower SF6 removal efficiency than that of the DBD reactor. In other words, different behavior between CF4 and SF6 removal efficiencies achieved with two different types of NTP reactors was found in this paper. To elucidate this interesting finding, the influences of the discharge power, the reactor temperature, the catalytic effect, the nature of pollutants, and the plasma characteristics of DBD and PBR were investigated. It is found that the last two factors are mainly responsible for the interesting finding. At the same discharge gap, it is well known that PBR possesses higher mean electron energy than nonpacked plasma reactor (like DBD). Nevertheless, the dissociative attachment reaction of SF6 : SF6 + e → SF5- + F plays an important role for SF6 removal at low-electron-energy region. Therefore, a nonpacked plasma reactor is more suitable for SF6 removal; on the contrary, a PBR with higher mean electron energy is favorable for CF4 abatement. The finding provides useful information on selecting an appropriate NTP reactor for removing a specific PFC. [ABSTRACT FROM AUTHOR]

This paper presents a new control method for cascaded connected H-bridge converter-based static compensators. These converters have: classically been commutated at fundamental line frequencies, but the evolution of power semiconductors has allowed the increase of switching frequencies and power ratings of these devices, permitting the use of pulsewidth modulation techniques. This paper mainly focuses on dc-bus voltage balancing problems and proposes a new control technique (individual voltage balancing strategy), which solves these balancing problems, maintaining the delivered reactive power equally distributed among all the H-bridges of the converter. [ABSTRACT FROM AUTHOR]

It has been recognized that effective fault detection techniques can help semiconductor manufacturers reduce scrap, increase equipment uptime, and reduce the usage of test wafers. Traditional univariate statistical process control charts have long been used for fault detection. Recently, multivariate statistical fault detection methods such as principal component analysis (PCA)-based methods have drawn increasing interest in the semiconductor manufacturing industry. However, the unique characteristics of the semiconductor processes, such as nonlin-earity in most batch processes, multimodal batch trajectories due to product mix, and process steps with variable durations, have posed some difficulties to the PCA-based methods. To explicitly account for these unique characteristics, a fault detection method using the k-nearest neighbor rule (FD-kNN) is developed in this paper. Because in fault detection faults are usually not identified and characterized beforehand, in this paper the traditional kNN algorithm is adapted such that only normal operation data is needed. Because the developed method makes use of the kNN rule, which is a nonlinear classifier, it naturally handles possible nonlinearity in the data. Also, because the FD-kNN method makes decisions based on small local neighborhoods of similar batches, it is well suited for multimodal cases. Another feature of the proposed FD-kNN method, which is essential for online fault detection, is that the data preprocessing is performed automatically without human intervention. These capabilities of the developed FD-kNN method are demonstrated by simulated illustrative examples as well as an industrial example. [ABSTRACT FROM AUTHOR]

Presents the table of contents for this issue of the publication. [ABSTRACT FROM PUBLISHER]

Editorial. Comments on the growth of the semiconductor manufacturing industry. Design and scheduling of wafer fabrication facility; Analysis of semiconductor manufacturing systems; Control of wafer processing equipment.

The purpose of this paper was to estimate the reduction efficiency of an abatement system for perfluorocarbon (PFC) gases produced during semiconductor manufacturing processes. The reduction efficiency currently used in the semiconductor industry, the destruction and removal efficiency (DRE), considers only the destruction ratio of PFC gases. A method estimating the reduction efficiency, which in addition to measure the destruction ratio also considers the energy consumption and byproducts produced during the treatment of PFC gases, was proposed in this paper; this efficiency was defined as the net reduction efficiency (NRE). For the estimation of the reduction efficiency, measurements were made using a plasma-wet type abatement system installed in an actual semiconductor manufacturing plant. The destruction ratio of the PFC gases was measured using Fourier transform infrared spectroscopy and quadrupole mass spectroscopy. The energy consumption was measured using an electricity meter. Based on these measurements, the DRE and the NRE of the PFC gases were calculated and compared. The results indicated that the DRE showed high reduction efficiency while the NRE showed lower values. [ABSTRACT FROM AUTHOR]

The rise of industry 4.0 and data-intensive manufacturing makes advanced process control (APC) applications more relevant than ever for process/production optimization, related costs reduction, and increased efficiency. One of the most important APC technologies is virtual metrology (VM). VM aims at exploiting information already available in the process/system under exam, to estimate quantities that are costly or impossible to measure. Machine learning (ML) approaches are the foremost choice to design VM solutions. A serious drawback of traditional ML methodologies is that they require a features extraction phase that generally limits the scalability and performance of VM solutions. Particularly, in presence of multi-dimensional data, the feature extraction process is based on heuristic approaches that may capture features with poor predictive power. In this paper, we exploit modern deep learning (DL)-based technologies that are able to automatically extract highly informative features from the data, providing more accurate and scalable VM solutions. In particular, we exploit DL architectures developed in the realm of computer vision to model data that have both spatial and time evolution. The proposed methodology is tested on a real industrial dataset related to etching, one of the most important semiconductor manufacturing processes. The dataset at hand contains optical emission spectroscopy data and it is paradigmatic of the feature extraction problem in VM under examination. [ABSTRACT FROM AUTHOR]

In the semi-conductor industry, factories ramp their production capacity in parallel with tool (machine) installations. Ramp capacity, and subsequently wafer starts, are aligned with additional installs of the most expensive tool. Subsequently, starts are set to the full capacity of that limiting toolset. In this paper, we argue that this may not be best method to maximize output over the ramp period and that by keeping ramp starts below constraint capacity, increased levels of cumulative output can be achieved for a desired planning horizon (e.g., the first year of production). A mathematical framework of the problem is provided to support our hypothesis, together with numerical examples and a set of simulation experiments. [ABSTRACT FROM AUTHOR]

Research and development (R&D) projects are crucial for semiconductor companies to maintain growth, profitability, and competitiveness. Integrated circuit (IC) design is capital intensive and continuously migrates to new technologies to meet various market demands. Moreover, the scheduling of selected R&D projects that enables technology roadmap involving complicated interrelationships, while competing for similar resources. Focusing on realistic needs, this paper aims to propose an integrated approach for selecting IC design projects for R&D portfolios and scheduling the selected projects simultaneously. In particular, a hybrid autotuning multiobjective genetic algorithm was developed to solve large sized problem instances. An empirical study was conducted at a leading IC design service company in Taiwan to test the validity of the proposed approach. The proposed algorithm was compared with conventional approaches for both convergence and diversity. The results have shown the practical viability of this approach in efficiently and effectively generating near-optimal portfolio alternatives for portfolio selection. The approach also enables the scheduling of the selected projects to achieve R&D portfolio objectives. The developed solution was fully implemented and adopted by the company. [ABSTRACT FROM PUBLISHER]

Deployment of an automatic visual inspection system in semiconductor industry has become increasingly popular than ever not only due to its relatively high value as a yield analysis tool of outgoing products but more importantly for the prevention of defect escapee. A lot of studies are done on the application of in-line defect scan but the application of outgoing wafer inspection at post-fab environment has been very limited and rarely found in literature. With rapid growth of automotive application in worldwide industry, the importance of quality of the wafer at die level has never been so critical. This paper provides a method for detection of bond pad discolorations at outgoing quality check especially in semiconductor industry. An effective method for detection of the bond pad discolorations was proposed. The advantages and disadvantages of the detection method are discussed. Factors that are affecting the performances of the detection method are also described and analyzed. [ABSTRACT FROM PUBLISHER]

Scheduling in a re-entrant manufacturing environment is a complex task that requires a scheduler to handle a larger number of uncertainties than in a traditional manufacturing environment. Many input control strategies and dispatching rules are applied to re-entrant processes to achieve fast and relatively effective solutions. However, due to the complexity of these processes, the dispatching rules currently employed in general flow shops do not guarantee the consistency of results despite the benefits of these rules. To address this issue, an extremely robust drum-buffer-rope-based releasing and holding scheduling method is proposed in this paper. An overview of the proposed method is presented, including the process by which the re-entrant process is reconfigured into independent flow shops and the balancing of the production loads among individual loops. Nine scheduling scenarios comprising different combinations of three loop load measurement parameters and three loop-balancing methods are employed to test the applicability and performance of the proposed method. [ABSTRACT FROM PUBLISHER]

A qualitative empirical study of 29 semiconductor manufacturer and supplier firms investigates the challenges associated with implementing lean practices that require broadly based collaboration across firms. The study's primary contribution is a model of the semiconductor manufacturing ecosystem, which shows how chipmakers, suppliers of enabling technologies, subsystem suppliers, and their respective competitors interact to develop the right technologies at the right time. The study finds that the biggest challenge to industry-wide collaboration is managing knowledge flows between users and suppliers in a manner that allows all parties to collaborate without losing competitive advantage. The paper also presents insights into how inter-organizational knowledge is created synchronously in the semiconductor industry. Finally, the paper makes suggestions as to how interfirm knowledge can be managed. [ABSTRACT FROM AUTHOR]

The article presents information about the papers presented in the International Symposium on Semiconductor Manufacturing (ISSM) 2004. The mission of ISSM is to continue to offer active communication while targeting the way the industry should aim. The criteria for the qualification of ISSM papers consists of three aspects, namely, significance, usefulness, and accuracy. Reviewers also check if a paper will contribute to innovation and improvement in the semiconductor industry. Among 127 papers accepted in ten technical areas of ISSM 2004, 15 papers were selected for Process Control and Yield Enhancement section.

In the semiconductor industry, the testing section has always played an important role. The testing section often requires engineers to judge the defect, which wastes a lot of time and cost. The accurate classification can provide useful information for engineers through neural networks. In this paper, we present a method for wafer map data augmentation and defect classification. Data augmentation is based on CNN encoder-decoder and the classification is based on depthwise separable convolutions. There are two datasets used, one is open dataset WM-811K and the other is built with a Taiwan company. We train two models with mobilenetV1 and V2 for the different datasets. The light-weight deep convolution can reduce model parameters and calculations, which is very efficient for the testing house with large production volumes. On two different data sets, our proposed method can reduce the number of parameters by 30% and 95%, and reduce the amount of calculation by 75% and 25%, respectively. The test accuracy of the first dataset is 93.95%. The second dataset test accuracy is 87.04%. After the data augmentation, accuracy is increased to 97.01% and 95.09%, respectively. [ABSTRACT FROM AUTHOR]

Three-dimensional integrated circuits (3-D ICs), which feature many benefits, such as high bandwidth and a high degree of integration, have recently received considerable attention from the semiconductor industry. However, these chips feature through-silicon vias (TSVs), which vertically connect multiple dies, and these TSVs may fail, resulting in a decreased yield. Unfortunately, previously proposed methods to repair TSVs cannot handle certain failure patterns. For example, existing techniques cannot repair clustered TSV faults, which commonly occur in practice. Furthermore, the number of signal TSVs typically determines the number of redundant TSVs, which may result in wasteful and redundant TSVs. In this paper, a new TSV repair scheme is proposed that replaces defective TSVs with redundant TSVs by utilizing the architecture of a cube, which can replace any face with any of the other faces. Both signal TSVs and redundant TSVs are placed in the face of cube, so any faulted TSVs can be replaced with redundant TSVs. The experimental results indicate that the new method guarantees 100% coverage with any number of signal TSVs and redundant TSVs. [ABSTRACT FROM AUTHOR]

In this paper, a supply chain simulation testbed for the semiconductor industry is proposed. We start by identifying requirements for such reference datasets, and then we identify the main building blocks. The nodes of the supply chain that represent semiconductor wafer fabrication facilities (wafer fabs) are built on a simulation model from the measurement and improvement of manufacturing capacity project. We present two techniques to reduce the modeling and computational burden that are able to deal with load-dependent cycle times in single front-end and back-end facilities and in the overall network. The first method models in detail only the bottlenecks in the nodes of the supply chain, while the second one uses empirical distributions for cycle time and throughput. The quality of these reduction techniques is assessed by comparing the detailed model and the models with a reduced level of detail. We present an application scenario for the testbed by simulating a semiconductor supply network. In addition, the usage of the testbed is discussed. [ABSTRACT FROM PUBLISHER]

E-beam inspection has become one of the most important tools for rapid yield ramp in the semiconductor industry, due to its ability to detect a wide range of defects in-line soon after their formation. This role expansion is due to the increasing difficulty in detecting defects in-line with other traditional methods as well as the continuing evolution of e-beam capability. In the last five years, the role of e-beam inspection has expanded from detection of electrically active, buried defects using voltage contrast inspection to also detection of many challenging physical defect types as well as systematic patterning defects. This paper reports on the impact of an important recent improvement in e-beam inspection tool capability, the availability of dramatically higher landing energies, and the benefits this improvement provides. These include detection of buried defects, a sharper image for detection of surface physical defects, minimization of wafer charge enabling much longer inspections, and material contrast. These advantages are illustrated through a number of examples. High landing energy can damage certain wafer surfaces and these concerns are also discussed. Overall, high landing energy is a powerful new tool in the e-beam inspection tool box which should be aggressively adopted. [ABSTRACT FROM AUTHOR]

The design options for low-voltage low-power (LVLP) applications are not limited to the circuit level, but it should start with the right choice of device technology and architecture. This paper presents a comparative study between a special structure of bulk MOSFET called the deep n-well protected device and the partially depleted silicon-on-insulator device. This paper shows the advantage of each device for different operation schemes while concentrating on the RF behavior for very low bias conditions. The study shows the lower limit for the bias conditions for the devices to correctly operate in RF. It also presents the effect of high temperature on the key figures of merit for dc and RF operations for high-performance and LVLP operation regimes. [ABSTRACT FROM AUTHOR]

In this paper, we have developed a new floating-gate-type Flash cell compact model based on the channel potential by using PSP metal-oxide-semiconductor description. Cell-to-cell coupling, Fowler–Nordheim tunneling, and new leakage current formulas have been implemented on Verilog-A compact model. The channel potential calculation of the PSP model enables accurate modeling of channel coupling and leakage currents which are associated with the boosted channel. In addition, the model parameter extraction procedure through 3-D technology computer-aided design (TCAD) and SPICE simulation is presented. The simulation results agree well with measured data of sub-20-nm nand cells. [ABSTRACT FROM AUTHOR]

This paper presents a decision-making model describing the automated material handling system (AMHS) variables that should be incorporated in the strategic planning process associated with the upcoming wafer size transitions. A literature review on AMHS technology facilitated the selection of critical variables, such as cycle time improvement, wafer transition costs, paying the bill, return on investment, productivity, equipment, and material. Several hypotheses were postulated and analyzed based on data gathered from an industry survey. Some of the findings include: companies involved in the transition of next wafer size should share the cost of development and implementation, and the next-generation AMHS technology will satisfy performance requirements of 450 mm fabs. This paper provides conclusions and recommendations that might assist managers in the strategic planning process. [ABSTRACT FROM PUBLISHER]

An atmospheric microwave plasma torch for the decomposition of \SF6 accompanying additive gases (\O2, compressed air) was investigated experimentally in this paper. Applied microwave power and additive gas species as effective parameters on destruction and removal efficiency (DRE) were considered. It was approved that compressed air is a more efficient additive gas for the removal of \SF6 compared to oxygen. Also, DRE is highly dependent on the variation of forward power. Highest efficiencies while using oxygen and compressed air as additive gases have been 98.4% and 99.1% (in 1100 W), respectively. In some case, the \N2 was also used with \SF6, resulting in a maximum efficiency (in 1100 W) of 99.4%. This paper approves that a microwave plasma torch sustained in atmospheric pressure can almost completely remove the \SF6 in semiconductor industry. [ABSTRACT FROM PUBLISHER]

Frequent monitoring in both tool and process is required to detect the quality issue early so as to improve the process stability of semiconductor manufacturing. However, more tool and process monitoring means more metrology operation cost and longer cycle time. Recently, a promising technology denoted virtual metrology (VM) has bloomed. VM can convert sampling inspection with metrology delay into real-time and on-line total inspection. Therefore, VM has now been designated by International SEMATECH Manufacturing Initiative and International Technology Road Map for Semiconductors as one of the focus areas for the next generation factory realization road map of the semiconductor industry. The authors have developed the so-called automatic virtual metrology (AVM) system to implement and deploy the VM operations automatically. The purpose of this paper is to develop a business model to measure the profitability of VM based on in-depth manufacturing practices and metrology operations required for semiconductor manufacturing. This paper also proposes a novel manufacturing system that integrates AVM into the manufacturing execution system (MES). The interfaces among AVM, other MES components, and run-to-run (R2R) modules in the novel manufacturing system are also defined such that the total quality inspection system can be achieved and the R2R capability can be migrated from lot-to-lot control to wafer-to-wafer control. [ABSTRACT FROM AUTHOR]

The semiconductor industry tends to constantly increase the performances of developed systems with an ever-shorter time-to-market. In this context, the conventional strategy for mixed-signal component design, which is based only on analog design effort, will no longer be suitable. In this paper, a digital correction technique is presented for analog-to-digital converters (ADCs). The idea is to use a lookup table (LUT) for the online correction of integral nonlinearity (INL). The main challenge for this kind of technique is the cost in time and resources to estimate the actual INL of the ADC needed to load the LUT. In this paper, we propose to extract INL with a very rapid procedure based on spectral analysis. We validate our technique on a 12-bit folding-and-interpolating ADC and we demonstrate that the correction is efficient for a large range of application fields. [ABSTRACT FROM AUTHOR]

This paper, for the first time, estimates the influences of the intrinsic-parameter fluctuations consisting of metal-gate work-function fluctuation (WKF), process-variation effect (PVE), and random-dopant fluctuation (RDF) on 16-nm-gate planar metal-oxide-semiconductor field-effect transistors (MOSFETs) and circuits. The WKF and RDF dominate the threshold-voltage fluctuation (σVth); however, the WKF brings less impact on the gate capacitance and the cutoff frequency due to the screening effect of the inversion layer. The fluctuation of timing characteristics depends on the σVth and is therefore proportional to the trend of σVth. The power fluctuation consisting of the dynamic, short-circuit, and static powers is further investigated. The total power fluctuation for the planar MOSFET circuits is 15.2%, which is substantial in the reliability of circuits and systems. The static power is a minor part of the total power; however, its fluctuation is significant because of the serious fluctuation of the leakage current. For an amplifier circuit, the high-frequency characteristics, the circuit gain, the 3-dB bandwidth, the unity-gain bandwidth power, and the power-added efficiency are explored consequently. Similar to the trend of the cutoff frequency, the PVE and RDF dominate both the device and circuit characteristic fluctuations due to the significant gate-capacitance fluctuations, and the WKF is less important at this simulation scenario. The extensive study assesses the fluctuations on circuit performance and reliability, which can, in turn, be used to optimize nanoscale MOSFETs and circuits. [ABSTRACT FROM AUTHOR]

Increasing yield and improving product quality are two important issues in the area of semiconductor manufacturing. The purpose of multivariate statistical process control is to improve process operations by quickly detecting process abnormalities and diagnosing the sources of the detected process abnormalities. The statistical-based multiway principal component analysis (PCA) method has drawn increasing interest in semiconductor manufacturing process monitoring. However, there are several drawbacks of this method, including future value estimation, limited number of batches, and non-Gaussian behavior of the process data. This paper proposes a new adaptive substatistical PCA-based method that can avoid future value estimation. By employing support vector data description, a new monitoring statistic is developed that has no Gaussian limitation of the process data. In addition, correlations among the new method, multimodel, and multiway PCA are detailed. Capabilities of the proposed method are demonstrated by an industrial example. [ABSTRACT FROM AUTHOR]

Editorial. Comments on issues related to semiconductor manufacturing at technology nodes below 70 nm. Improvement in the performance, reliability and functionality of semiconductor products; Reduction of time in the market of products; Achievement of overall cost reduction.

As the costs of building a new wafer fab increase, a detailed simulation model representing the production operations, the tools, the automated material handling systems (AMHS), and the tool-AMHS interactions is needed for accurately planning the capacity of these facilities. The problem is that it currently takes too long to build, experiment, and analyze a sufficiently detailed model of a fab. The key for building accurate and computationally efficient fab models is to decide on the right amount of model details, specifically those details representing the equipment capacity and the AMHS. This paper identifies a method for classifying a fab model by the level of capacity detail, the level of AMHS detail, or the level of capacity/AMHS detail. Within the capacity! AMHS modeling level, our method further differentiates between detailed integrated capacity/AMHS models and abstract coupled capacity/AMHS models. The proposed classification method serves as the basis of a framework that helps users select the system components to be modeled within a desired level of detail. This research also provides a review of past-published literature summarizing the work done at each of the proposed fab modeling levels. A case study comparing the performance between an integrated capacity/AMHS model and a coupled capacity/AMHS model is presented. The study demonstrates that the coupled model generates cycle time estimates that are not statistically different than those generated by the integrated model. This paper also shows that the coupled model can improve CPU time by approximately 98% in relation to the integrated model. [ABSTRACT FROM AUTHOR]

Manufacturing productivity in the semiconductor industry is a key factor in determining the competitiveness of manufacturers. In order to enhance productivity, evaluating the productivity of wafer maps prior to production and optimizing the productivity of wafer maps is one of the most effective solutions. The productivity of a wafer map is evaluated in advance by considering various factors affecting wafer productivity such as: gross dies, shot counts, lithography throughputs, mask field occupancy (MFO), prices, etc. Manufacturing process information is not determined at the initial wafer map design stage. Predicting the yield of new wafer maps before fabrication is a difficult challenge due to lack of process information. However, a yield prediction model is required to precisely evaluate the productivity of new wafer maps, because the yield is directly related to the productivity and the design of wafer map affects the yield. In this paper, we propose a novel yield prediction model based on deep learning algorithms. Our approach exploits spatial relationships among positions of dies on a wafer and die-level yield variations collected from a wafer test without process parameters. By modeling these spatial features, the accuracy of yield prediction significantly increased. Furthermore, experimental results showed that the proposed yield model and approach helps to design wafer maps with up to 8.59% higher productivity. [ABSTRACT FROM AUTHOR]

To recruit and retain high-potential talent is critical for semiconductor companies to maintain competitive advantages in a modern knowledge-based economy. Conventional personnel selection methodologies focusing on static work and job analysis will no longer be appropriate for knowledge workers in high-tech industries. This paper aims to develop an effective data mining approach based on Rough Set Theory to explore and analyze human resource data for personnel selection and human capital enhancement. An empirical study was conducted in a leading semiconductor company in Taiwan to estimate the validity of the proposed approach for predicting work behaviors including performance and resignation. The results showed that latent knowledge can be discovered as a basis to derive specific recruitment and human resource management strategies. In particular, 29 rules have been adopted as references for recruiting the right talent. This paper concludes with discussions of empirical findings and future research directions. [ABSTRACT FROM AUTHOR]