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In the era of big data, the memory wall between the processor and the memory as well as leakage current have become major bottlenecks of the traditional CMOS-based Von-Neumann computer architecture. Computing-in-memory (CiM) based on non-volatile memories (NVMs) is considered a promising method to solve the above-mentioned issues in computing systems. In this article, we propose a CiM platform based on spin-transfer torque magnetic random access memory (STT-MRAM). On the basis of the conventional CiM with AND/OR logic functions, the full-adder (FA) arithmetic operation is achieved with slight circuits modification by exploiting majority logic. Due to the parallel processing of carry and sum operations in multi-bit FA operation, the latency overhead caused by the two-step scheme is acceptable. The hybrid spintronic/CMOS simulations on the 40 nm technology node prove the functionality and performance of the proposed CiM platform. [ABSTRACT FROM AUTHOR]

Recent progress has demonstrated that current-induced domain wall motion (CIDWM) is able to achieve efficient and ultrafast magnetic switching in the case of spin–orbit torque (SOT) and Dzyaloshinskii–Moriya interaction (DMI). CIDWM-based devices are taken as promising candidates for the next-generation nonvolatile artificial neurons and synapses due to its excellent programmability, fast operation speed, low write power, and so on. In this article, we present a physics-based model of CIDWM magnetic tunnel junction (MTJ), which exhibits high performance based on experimental results. The proposed model integrates the CIDWM dynamics and nanowire MTJ resistance, showing great agreement with extensive physical simulation. A learning circuit based on CIDWM-MTJ, as a hybrid MTJ/CMOS circuit example, has been designed and simulated to validate its functionality. The proposed SPICE-compatible compact model will be useful for high-performance circuit and system evaluation and is expected to promote the research and development of CIDWM-based spintronics devices. [ABSTRACT FROM AUTHOR]

The conductivity of spin field-effect transistor (spin-FET) can be modulated by controlling the spin degree of freedom; therefore, emerging low-power applications can be explored. In this paper, we propose a novel device called multi-gate spin-FET where multi-gate voltages can successively modulate the spin of the electrons. Various logic functions can be implemented with multi-gate spin-FET by setting the appropriate channel lengths. First, we present an electrical model of the multi-gate spin-FET which considers the physical mechanisms and the fitting of experimental results. The availability of the electrical model is validated by the dc simulation. Afterward, typical logic circuits are designed with the multi-gate spin-FET, including NAND gate, XOR gate, full adder, and a representative three-input logic gate. Transient simulation results validate the functional behaviors of these logic circuits. Finally, based on an analysis of power consumption, we conclude that the multi-gate spin-FET is a more energy-efficient device compared with the conventional CMOS FET. [ABSTRACT FROM AUTHOR]

Magnetic random access memory (MRAM) is experimentally proved intrinsically immune to radiation effects including heavy-ion irradiation and total ion dose as the data are represented by the spin instead of charges. Hence, it is considered as a promising candidate for aerospace and avionic electronics. However, its CMOS peripheral read/write circuits are much more vulnerable to radiation-induced single-event upset (SEU) and double-node upset (DNU) induced by charge sharing. This paper presents a novel radiation-hardening design of the peripheral circuitry for spin orbit torque (SOT)-MRAM to address abovementioned issues effectively. Transient simulations are performed based on a physics-based SOT-magnetic tunnel junction compact model and a 65 nm CMOS design kit. Simulation results validate that the proposed hardening read/write circuits are strongly robust against SEUs and DNUs. Furthermore, the proposed hardening read circuit shows the improvement of hardware area and reliability compared with the previous works. [ABSTRACT FROM AUTHOR]

Spintronics-based devices and circuits attract massive research interest from both academia and industry. A number of the devices and logic circuits have been proposed such as spin-based magnetic tunnel junction and all spin logic gate. A fundamental spin-based device, spin field-effect transistor (spin-FET) is one of the most interesting spin-based devices to address the power issue of semiconductor transistors which is still a research focus. In this paper, we first present an electrical model for the spin-FET based on both theoretical and experimental results. The theories of spin injection and detection are considered by a current driver of the spin-FET. Gate voltage modulation following Datta–Das theory is combined with the experimental results from several works of literature. Afterward, through the dc analysis of two spin-FETs with different channel materials, we demonstrate that the channel using InAs is a better choice to make a feasible spin-FET. The channel length is also optimized by the comparison of simulation results. Finally, a local geometry spin-FET model suitable for logic design is implemented with Verilog-A language and integrated on Cadence platform. Using our model, a low-power inverter is designed based on the concept of complementary spin-FET, and a logic circuit is proposed to implement AND and NOR logic functions. Simulation results validate the behaviors of the logic circuits and availability of our model. [ABSTRACT FROM AUTHOR]