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In the era of big data, the memory wall between the processor and the memory as well as leakage current have become major bottlenecks of the traditional CMOS-based Von-Neumann computer architecture. Computing-in-memory (CiM) based on non-volatile memories (NVMs) is considered a promising method to solve the above-mentioned issues in computing systems. In this article, we propose a CiM platform based on spin-transfer torque magnetic random access memory (STT-MRAM). On the basis of the conventional CiM with AND/OR logic functions, the full-adder (FA) arithmetic operation is achieved with slight circuits modification by exploiting majority logic. Due to the parallel processing of carry and sum operations in multi-bit FA operation, the latency overhead caused by the two-step scheme is acceptable. The hybrid spintronic/CMOS simulations on the 40 nm technology node prove the functionality and performance of the proposed CiM platform. [ABSTRACT FROM AUTHOR]

Spin-transfer torque magnetic random access memory (STT-MRAM) offers nonvolatility, good scalability, high speed, and low-power benefits. Multilevel cell (MLC) is an efficient technology to boost the storage density of the STT-MRAM. However, the conventional MLC structure is not suitable for more than 2-b storage due to inefficient multistep read/write operations. In this article, combining the emerging spin-orbit torque (SOT) and STT mechanisms, we propose a novel STT/SOT hybrid triple-level cell (TLC) MRAM cell structure. Corresponding write and read schemes are designed for this hybrid bit-cell to achieve low-cost operations. Unlike the regular stacked TLC, 3-b data can be written in two steps in the proposed cell structure, and be read in parallel with the assistance of SOT. Simulation results show that the proposed structure achieves 32% and 43% savings on write delay and energy consumption, respectively. Monte Carlo statistic simulation results indicate 1.4 × improvement in sensing margin as well. [ABSTRACT FROM AUTHOR]

With the process node further scaling down, the bit cell of magnetic random access memory (MRAM) device suffers from severe failure and reliability problems due to its process variation. In this article, we explored the variability of a promising toggle spin torques MRAM (TST-MRAM) in detail, which achieves ultrafast switching speed and high endurance and is expected to be applied as upper-level caches. Our research is conducted with a 14 nm FinFET design kit, the basic performance of TST-MRAM and different pulse conditions are explored, and then the variation effect of device parameters is discussed and compared in detail as well as the write error rate (WER) under different voltages. The results demonstrate that the variation of access transistors dominates the variability, where the transistor in the spin–orbit torque (SOT) branch has a greater negative impact than the transistor in the spin transfer torque (STT) branch. To further reduce WER, a better structure with diodes of bit cell is proposed. [ABSTRACT FROM AUTHOR]

As the speed gap of the modern processor and the off-chip main memory enlarges, on-chip cache capacity increases to sustain the performance scaling. As a result, the cache power occupies a large portion of the total power budget. Spin transfer torque magnetic memory (STT-MRAM) is proposed as a promising solution for the low power cache design due to its high integration density and ultralow leakage power. Nevertheless, the high write power and latency of STT-MRAM become new barriers for the commercialization of this emerging technology. In this paper, we investigate the thermal effect on the access performance of STT-MRAM, and observe that the temperature can affect the write delay and energy significantly. Then, we explore the nonuniform cache access (NUCA) design of the chip-multiprocessors with STT-MRAM-based last level cache (LLC). A thermal aware data migration policy, called “Thermosiphon,” which takes advantage of the thermal property of STT-MRAM, is proposed to reduce the LLC write energy. This policy splits the LLC into different regions dynamically based on the thermal distribution monitored by thermal sensors available on-chip, and adaptively migrates write intensive data among different thermal regions considering the thermal gradient. Compared to the conventional NUCA design, our proposed design can save 41.2% write energy at most and 13.01% on average with negligible hardware overhead. [ABSTRACT FROM AUTHOR]