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This article considers the quasisynchronization of memristive neural networks (MNNs) with communication delays via event-triggered impulsive control (ETIC). In view of the limited communication and bandwidth, we adopt a novel switching event-triggered mechanism (ETM) that not only decreases the times of controller update and the amount of data sent out but also eliminates the Zeno behavior. By using an appropriate Lyapunov function, several algebraic conditions are given for quasisynchronization of MNNs with communication delays. More important, there is no restriction on the derivation of the Lyapunov function, even if it is an increasing function over a period of time. Then, we further propose a switching ETM depending on communication delays and aperiodic sampling, which is more economical and practical and can directly avoid Zeno behavior. Finally, two simulations are presented to validate the effectiveness of the proposed results. [ABSTRACT FROM AUTHOR]

Due to the natural nonlinearity and unique memory characteristics, memristors are promising candidates for the construction of multiscroll attractors having better application potential in the field of information encryption than the traditional double-scroll attractors. This article proposes a novel memristive multidouble-scroll Chua’s system (MMDSCS) via coupling a nonideal flux-controlled memristor with multipiecewise-linear memductance function in Chua’s system directly. Specially, any number of multidouble-scroll chaotic attractors can be generated through adjusting the internal parameters of the memristor conveniently and without changing the original system’s nonlinearity. Moreover, the amount of double scrolls is also closely related to the strength of the memristive coupling. Another striking highlight is that infinite initial offset-boosted coexisting Chua’s double-scroll attractors with the same shape are produced with the variation of the memristor initial conditions, indicating the emergence of an intriguing phenomenon of homogeneous extreme multistability. This unique property and its formation mechanism are investigated in detail using phase portraits, bifurcation diagrams, Lyapunov exponents, time series, and attraction basins. Furthermore, hardware experiments based on the field-programmable gate array are carried out to confirm the numerical simulations. Finally, an image encryption scheme is designed based on the memristor initial offset boosting dynamics from a perspective of engineering application. In comparison with the existing memristive Chua’s systems, the proposed MMDSCS has many merits, such as multidouble-scroll attractors, memristor initial-controlled chaotic sequences with controllability, good robustness, and high security performance, which is more practical in applications involving information confidential communication. [ABSTRACT FROM AUTHOR]

This article investigates global exponential stabilization (GES) of Takagi–Sugeno (T–S) fuzzy memristive neural networks with multiple time-varying delays (DFMNNs) via intermittent control strategy. By resorting to differential inclusion theory, comparison means, and inequality techniques, some results are developed to ensure GES of the underlying DFMNNs via a fuzzy intermittent state feedback control law within the sense of Filippov. The outcome is generalized to GES of FMNNs with infinite distributed time delays. Additionally, the global exponential stability of FMNNs with discrete time-varying delays is explored in terms of 1-norm. The derived conditions herein contain certain existing ones as special cases. Finally, three examples are presented to illuminate the validness of the outcomes. [ABSTRACT FROM AUTHOR]

This article investigates hardware implementation of hierarchical temporal memory (HTM), a brain-inspired machine learning algorithm that mimics the key functions of the neocortex and is applicable to many machine learning tasks. Spatial pooler (SP) is one of the main parts of HTM, designed to learn the spatial information and obtain the sparse distributed representations (SDRs) of input patterns. The other part is temporal memory (TM) which aims to learn the temporal information of inputs. The memristor, which is an appropriate synapse emulator for neuromorphic systems, can be used as the synapse in SP and TM circuits. In this article, a memristor-based SP (MSP) circuit structure is designed to accelerate the execution of the SP algorithm. The presented MSP has properties of modeling both the synaptic permanence and the synaptic connection state within a single synapse, and on-device and parallel learning. Simulation results of statistic metrics and classification tasks on several real-world datasets substantiate the validity of MSP. [ABSTRACT FROM AUTHOR]

Memristor-based chaotic systems have been received great attention from researchers in the last decade. This brief investigates parameter identification of a memristor-based chaotic system (proposed by Muthuswamy in 2010). Uncertain parameter identification has not been studied yet for memristor-based chaotic systems. Using the Lyapunov stability theory and Barbălat lemma, two theorems are established to identify uncertain parameters of the system under the following two cases: i) the memductance is unknown; ii) capacitances and inductances are unknown. Finally, numerical simulations are carried out and the results show that the proposed parameter identification methods are effective. [ABSTRACT FROM AUTHOR]

Existing deep neural networks (DNNs) are computationally expensive and memory intensive, which hinder their further deployment in novel nanoscale devices and applications with lower memory resources or strict latency requirements. In this paper, a novel approach to accelerate on-chip learning systems using memristive quantized neural networks (M-QNNs) is presented. A real problem of multilevel memristive synaptic weights due to device-to-device (D2D) and cycle-to-cycle (C2C) variations is considered. Different levels of Gaussian noise are added to the memristive model during each adjustment. Another method of using memristors with binary states to build M-QNNs is presented, which suffers from fewer D2D and C2C variations compared with using multilevel memristors. Furthermore, methods of solving the sneak path issues in the memristive crossbar arrays are proposed. The M-QNN approach is evaluated on two image classification datasets, that is, ten-digit number and handwritten images of mixed National Institute of Standards and Technology (MNIST). In addition, input images with different levels of zero-mean Gaussian noise are tested to verify the robustness of the proposed method. Another highlight of the proposed method is that it can significantly reduce computational time and memory during the process of image recognition. [ABSTRACT FROM AUTHOR]

This paper investigates the quasi-synchronization of delayed memristive neural networks (MNNs) via a novel hybrid impulsive control algorithm which combines time-triggered and event-triggered impulsive control. The relationship between a predesigned non-negative auxiliary function and a given exponentially decreasing threshold function is used to describe the switching. Under this novel controller, sufficient conditions for the quasi-synchronization are derived by the impulsive differential inequality. In addition, by choosing appropriate parameters or initial conditions such that the initial value of the non-negative auxiliary function is less than that of the event-triggered function, the quasi-synchronization can be realized theoretically as long as the event-triggered impulsive intensity is less than 1. This greatly reduces the conservatism of the existing quasi-synchronization results. Furthermore, the event-triggered rules can avoid the Zeno behavior as long as the event-triggered impulsive intensity is less than 1. This hybrid mechanism can reduce the amount of impulsive control and lessen the network communication. Finally, one example is given to illustrate the validness of the obtained results. [ABSTRACT FROM AUTHOR]

This paper presents a complete solution for the hardware design of a memristor-based long short-term memory (MLSTM) network. Throughout the design process, we fully consider the external and internal structures of the long short-term memory (LSTM), both of which are efficiently implemented by memristor crossbars. In the specific design of the internal structure, the parameter sharing mechanism is used between the LSTM cells to minimize the hardware design scale. In particular, we designed a circuit that requires only one memristor crossbar for each unit in the LSTM cell. The activation function, including sigmoid and tanh (hyperbolic tangent function), involved in each unit is approximated by a piecewise function, which is designed with the corresponding hardware. To verify the effectiveness of the system we designed, we test it on IMDB and SemEval datasets. Considering the huge impact of the dimensions of the input data on the scale of the hardware design, we use word2vector instead of one-hot encoding for the input data encoding. With the parameter sharing mechanism, the transformed vectors are input in different periods, so only 65 memristive crossbars are needed in the entire system to complete the sentiment analysis of the input text. The experimental results verify the effectiveness of our proposed MLSTM system. [ABSTRACT FROM AUTHOR]

This paper proposes a unified framework to design sliding-mode control for stabilization of delayed memristive neural networks (DMNNs) with external disturbances. Under the presented framework, finite-time stabilization, and fixed-time stabilization of the controlled DMNNs can be, respectively, obtained by choosing different values for a specific control parameter. It is proved that the system responses can be made reaching the designed sliding-mode surface in finite and fixed time, and then stay on it. Moreover, it also illustrates that the inevitable external disturbances can be rejected by the designed sliding-mode control. Finally, the efficiency and superiority of the obtained main results are verified by comparisons with related works and numerical simulations. [ABSTRACT FROM AUTHOR]

This article investigates the global exponential stabilization (GES) of inertial memristive neural networks with discrete and distributed time-varying delays (DIMNNs). By introducing the inertial term into memristive neural networks (MNNs), DIMNNs are formulated as the second-order differential equations with discontinuous right-hand sides. Via a variable transformation, the initial DIMNNs are rewritten as the first-order differential equations. By exploiting the theories of differential inclusion, inequality techniques, and the comparison strategy, the $p$ th moment GES ($p\geq 1$) of the addressed DIMNNs is presented in terms of algebraic inequalities within the sense of Filippov, which enriches and extends some published results. In addition, the global exponential stability of MNNs is also performed in the form of an M-matrix, which contains some existing ones as special cases. Finally, two simulations are carried out to validate the correctness of the theories, and an application is developed in pseudorandom number generation. [ABSTRACT FROM AUTHOR]

Most memristor-based Pavlov associative memory neural networks strictly require that only simultaneous food and ring appear to generate associative memory. In this article, the time delay is considered, in order to form associative memory when the food stimulus lags behind the ring stimulus for a certain period of time. In addition, the rate of learning can be changed with the length of time between the ring stimulus and food stimulus. A memristive neural network circuit that can realize Pavlov associative memory with time delay is designed and verified by the simulation results. The designed circuit consists of a synapse module, a voltage control module, and a time-delay module. The functions, such as learning, forgetting, fast learning, slow forgetting, and time-delay learning, are implemented by the circuit. The Pavlov associative memory neural network with time-delay learning provides a reference for further development of the brain-like systems. [ABSTRACT FROM AUTHOR]

This paper focuses on Lagrange exponential stability and finite-time stabilization of Takagi–Sugeno (T–S) fuzzy memristive neural networks with discrete and distributed time-varying delays (DFMNNs). By resorting to theories of differential inclusions and the comparison strategy, an algebraic condition is developed to confirm Lagrange exponential stability of the underlying DFMNNs in Filippov’s sense, and the exponentially attractive set is estimated. When external input is not considered, global exponential stability of DFMNNs is derived directly, which includes some existing ones as special cases. Furthermore, finite-time stabilization of the addressed DFMNNs is analyzed by exploiting inequality techniques and the comparison approach via designing a nonlinear state feedback controller. The boundedness assumption of activation functions is removed herein. Finally, two simulations are presented to demonstrate the validness of the outcomes, and an application is performed in pseudorandom number generation. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel computational architecture of memristor-based echo state network (MESN) with the online least mean square (LMS) algorithm. Newman and Watts small-world network is adopted for the topological structure of MESN network with memristive neural synapses. In the MESN network, the state matrix of the reservoir layer, which is obtained by raising the dimension of input data, is utilized as an input of the LMS algorithm to train the output weight matrix on chip. After certain iterations, the resistance value of memristor is adjusted to a constant. Thus, the final weight output matrix is obtained. To verify the effectiveness of the proposed MESN network, car evaluation and short-term power load forecasting are employed with the effect evaluation of the node number and the connectivity degree of the reservoir layer. The research provides a novel way to design neuromorphic computing systems. [ABSTRACT FROM AUTHOR]

Back propagation (BP) based on stochastic gradient descent is the prevailing method to train multilayer neural networks (MNNs) with hidden layers. However, the existence of the physical separation between memory arrays and arithmetic module makes it inefficient and ineffective to implement BP in conventional digital hardware. Although CMOS may alleviate some problems of the hardware implementation of MNNs, synapses based on CMOS cost too much power and areas in very large scale integrated circuits. As a novel device, memristor shows promises to overcome this shortcoming due to its ability to closely integrate processing and memory. This paper proposes a novel circuit for implementing a synapse based on a memristor and two MOSFET tansistors (p-type and n-type). Compared with a CMOS-only circuit, the proposed one reduced the area consumption by 92%–98%. In addition, we develop a fuzzy method for the adjustment of the learning rates of MNNs, which increases the learning accuracy by 2%–3% compared with a constant learning rate. Meanwhile, the fuzzy adjustment method is robust and insensitive to parameter changes due to the approximate reasoning. Furthermore, the proposed methods can be extended to memristor-based multilayer convolutional neural network for complex tasks. The novel architecture behaves in a human-liking thinking process. [ABSTRACT FROM AUTHOR]

The existing results of passivity for neural networks mainly concentrated on first-order derivative of the states, whereas it is also significant to study the passivity with high-order derivative. In this paper, a class of memristor-based inertial neural networks (MINNs) with external inputs and outputs are concerned. First, by choosing appropriate variable transformation, the original networks are rewritten as first-order differential equations. Then a criterion of passivity for the MINNs is presented by nonsmooth analysis and linear matrix inequality (LMI) techniques, which could also result in NP-hard problem since it needs at least exponential-time to solve the passivity condition. Meanwhile, based on the obtained passivity criterion, asymptotic stability criterion is accordingly derived for MINNs. In order to avoid the NP-hard problem, we employ matrix-analysis-techniques with the property that the difference-matrix between the given matrix and the proposed matrix is seminegative definite. Then the time complexity for solving the proposed passivity criterion is reduced to constant-time with respect to the number of LMIs. Robust passivity for MINNs is also studied for bounded uncertain parameters. The MINN widens the application ranges for designing neural networks. Finally, relevant simulation examples are given to show the effectiveness of the obtained results. [ABSTRACT FROM AUTHOR]

The multivalued memory achieved with memristors is a promising approach to enhance the memory density. Effective and compact methods of reading and writing for multivalued memories can significantly improve the performance of circuits. In this paper, we present a compact and efficient scheme of reading and writing for two memristors per transistor-based multivalued memory. With the VTEAM model of the memristor, the verification of feasibility of our reading operations and writing operations for multivalued memory is achieved through HSPICE simulation. [ABSTRACT FROM AUTHOR]

This paper proposes a novel memristor-based multiplexer implemented by using NOT-material implication. The proposed design can be extended to arbitrary ${N}$ -bit inputs and the enable-port can be added to improve its structure. Furthermore, this structure can be applied in the cascade circuit and crossbar array. A novel peripheral read circuit is introduced to overcome the problem that it is difficult to read out the operation results stored in crossbar array with large scales. The feasibility and correctness of our design is verified by the HSPICE simulation results with voltage threshold adaptive memristor model. [ABSTRACT FROM AUTHOR]

Due to the conventional look-up-table (LUT) using the static random access memory (SRAM) cell, field programmable gate arrays (FPGAs) almost reach the limitation in term of the density, speed, and configuration overhead. This paper proposes an improved memristor-based LUT (MLUT) circuit which is compatible with the mainstream LUT circuit in FPGA. Any arbitrary combined logic functions can be implemented in the MLUT through specific configurations. Then the MLUT shows superior advantages over the conventional LUT such as smaller area overhead and fewer data transmission. As a case study, a one-bit full adder is simulated to verify that the design is of practice in PSPICE. Moreover, the adder can be cascaded into multibit full adder demonstrating competitiveness against the conventional configurable logic block in FPGA technology. MLUT can be a candidate to replace the conventional SRAM-based LUT and further improves the performance of FPGAs. [ABSTRACT FROM PUBLISHER]

This brief studies the sliding-mode control (SMC) scheme of uncertain memristive Chua's circuits via the event-based method. The sliding-mode controller possesses the advantage of its strong robustness and fast response over other control techniques. However, this controller is generally required to be executed in a continuous manner in order to make the trajectories of augmented systems drive onto the sliding surface in a finite time. In practice, these control methods are performed in a digital form. Thus, this brief proposes the event-based SMC which is executed only when necessary. Meanwhile, the existence of the lower bound for interexecution time is derived in this brief. Finally, a case study is conducted to illustrate the effectiveness of the derived results. [ABSTRACT FROM PUBLISHER]