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In the era of big data, the memory wall between the processor and the memory as well as leakage current have become major bottlenecks of the traditional CMOS-based Von-Neumann computer architecture. Computing-in-memory (CiM) based on non-volatile memories (NVMs) is considered a promising method to solve the above-mentioned issues in computing systems. In this article, we propose a CiM platform based on spin-transfer torque magnetic random access memory (STT-MRAM). On the basis of the conventional CiM with AND/OR logic functions, the full-adder (FA) arithmetic operation is achieved with slight circuits modification by exploiting majority logic. Due to the parallel processing of carry and sum operations in multi-bit FA operation, the latency overhead caused by the two-step scheme is acceptable. The hybrid spintronic/CMOS simulations on the 40 nm technology node prove the functionality and performance of the proposed CiM platform. [ABSTRACT FROM AUTHOR]

Recent progress has demonstrated that current-induced domain wall motion (CIDWM) is able to achieve efficient and ultrafast magnetic switching in the case of spin–orbit torque (SOT) and Dzyaloshinskii–Moriya interaction (DMI). CIDWM-based devices are taken as promising candidates for the next-generation nonvolatile artificial neurons and synapses due to its excellent programmability, fast operation speed, low write power, and so on. In this article, we present a physics-based model of CIDWM magnetic tunnel junction (MTJ), which exhibits high performance based on experimental results. The proposed model integrates the CIDWM dynamics and nanowire MTJ resistance, showing great agreement with extensive physical simulation. A learning circuit based on CIDWM-MTJ, as a hybrid MTJ/CMOS circuit example, has been designed and simulated to validate its functionality. The proposed SPICE-compatible compact model will be useful for high-performance circuit and system evaluation and is expected to promote the research and development of CIDWM-based spintronics devices. [ABSTRACT FROM AUTHOR]

Thanks to the progress in nonvolatile (NV) devices, such as magnetic tunnel junctions and phase change memories, various NV logic blocks have recently been proposed to overcome energy/delay bottlenecks caused by von Neumann computing architecture. The ferroelectric tunnel memristor (FTM) is an emerging NV multilevel device and was recently reported to show excellent performance. In this paper, we demonstrated that the short-circuit effect in an FTM provides the opportunity to design a novel FTM-based Boolean logic block. This block is composed of an FTM and a load resistor. Unlike classical schemes, where at least two cells are required as operands, our FTM-based block implements logic operation inside a single memristor. With a compact model of an FTM, transient simulation is performed to validate NAND and NOR logic functions. Finally, we provide the method of performance optimization and discuss the advantages/disadvantages of the proposed logic block to summarize our work. [ABSTRACT FROM AUTHOR]

In the current big data era, the memory wall issue between the processor and the memory becomes one of the most critical bottlenecks for conventional Von-Newman computer architecture. In-memory processing (IMP) or near-memory processing (NMP) paradigms have been proposed to address this problem by adding a small amount of processing units inside/near the memory. Unfortunately, although intensively studied, prior IMP/NMP platforms are practically unsuccessful because of the fabrication complexity and cost efficiency by integrating the processing units and memory on the same chip. Recently, emerging nonvolatile memories provide new possibility for efficiently implementing the IMP/NMP paradigm. In this paper, we propose a cost-efficient IMP/NMP solution in spin-transfer torque magnetic random access memory (STT–MRAM) without adding any processing units on the memory chip. The key idea behind the proposed IMP/NMP solution is to exploit the peripheral circuitry already existing inside memory (or with minimal changes) to perform bitwise logic operations. Such an IMP/NMP platform enables rather fast logic operations as the logic results can be obtained immediately through just a memory-like readout operation. Memory read and logics not, and/nand, and or/nor operations can be achieved and dynamically configured within the same STT–MRAM chip. Functionality and performance are evaluated with hybrid simulations under the 40 nm technology node. [ABSTRACT FROM AUTHOR]

Spin transfer torque-based magnetic random access memory (STT-MRAM) is considered as one of the most promising candidates for the next generation of nonvolatile memories; however, its storage density and reliability are currently uncompetitive compared with other nonvolatile memories (e.g., NAND flash). In this paper, a dual-functional memory cell structure, named DFSTT-MRAM, is proposed by stacking multiple magnetic tunnel junctions (MTJs) on top of the CMOS access transistor. In such a structure, the cell can be dynamically configured between two possible functional modes, i.e., high-reliability mode (HR-mode) and multilevel cell mode (MLC-mode), based on the data requirements of the addressed applications. The DFSTT-MRAM cell was electrically modeled based on the perpendicular magnetic anisotropy CoFeB/MgO/CoFeB MTJ integrating the STT stochastic switching behaviors. Transient and Monte Carlo simulations were then performed to evaluate its MLC functionality and reliability performance. Our evaluation results show that the DFSTT-MRAM cell can indeed realize MLC capability providing proper write/read control at the MLC-mode and enhance the intrinsic cell reliability by several orders of magnitude when operating at the HR-mode. This cell structure provides a flexible memory cell design for future advanced applications, such as high-density nonvolatile memory and neuromorphic circuits. [ABSTRACT FROM AUTHOR]

With the process node further scaling down, the bit cell of magnetic random access memory (MRAM) device suffers from severe failure and reliability problems due to its process variation. In this article, we explored the variability of a promising toggle spin torques MRAM (TST-MRAM) in detail, which achieves ultrafast switching speed and high endurance and is expected to be applied as upper-level caches. Our research is conducted with a 14 nm FinFET design kit, the basic performance of TST-MRAM and different pulse conditions are explored, and then the variation effect of device parameters is discussed and compared in detail as well as the write error rate (WER) under different voltages. The results demonstrate that the variation of access transistors dominates the variability, where the transistor in the spin–orbit torque (SOT) branch has a greater negative impact than the transistor in the spin transfer torque (STT) branch. To further reduce WER, a better structure with diodes of bit cell is proposed. [ABSTRACT FROM AUTHOR]