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In the era of big data, the memory wall between the processor and the memory as well as leakage current have become major bottlenecks of the traditional CMOS-based Von-Neumann computer architecture. Computing-in-memory (CiM) based on non-volatile memories (NVMs) is considered a promising method to solve the above-mentioned issues in computing systems. In this article, we propose a CiM platform based on spin-transfer torque magnetic random access memory (STT-MRAM). On the basis of the conventional CiM with AND/OR logic functions, the full-adder (FA) arithmetic operation is achieved with slight circuits modification by exploiting majority logic. Due to the parallel processing of carry and sum operations in multi-bit FA operation, the latency overhead caused by the two-step scheme is acceptable. The hybrid spintronic/CMOS simulations on the 40 nm technology node prove the functionality and performance of the proposed CiM platform. [ABSTRACT FROM AUTHOR]

Recent progress has demonstrated that current-induced domain wall motion (CIDWM) is able to achieve efficient and ultrafast magnetic switching in the case of spin–orbit torque (SOT) and Dzyaloshinskii–Moriya interaction (DMI). CIDWM-based devices are taken as promising candidates for the next-generation nonvolatile artificial neurons and synapses due to its excellent programmability, fast operation speed, low write power, and so on. In this article, we present a physics-based model of CIDWM magnetic tunnel junction (MTJ), which exhibits high performance based on experimental results. The proposed model integrates the CIDWM dynamics and nanowire MTJ resistance, showing great agreement with extensive physical simulation. A learning circuit based on CIDWM-MTJ, as a hybrid MTJ/CMOS circuit example, has been designed and simulated to validate its functionality. The proposed SPICE-compatible compact model will be useful for high-performance circuit and system evaluation and is expected to promote the research and development of CIDWM-based spintronics devices. [ABSTRACT FROM AUTHOR]

Ultrahigh-speed magnetization switching mechanism is strongly pursued, as it can improve the write performance of the magnetic random access memory (MRAM) and further extend the application area of spintronics. Currently, a well-studied switching mechanism is the spin transfer torque (STT), whose speed, however, is limited by an intrinsic incubation delay. Recently, spin–orbit torque (SOT) was proposed to solve the speed bottleneck of the STT. In this paper, we evaluate the potential of two types of SOT-MRAMs, whose data can be ultrafast written based on the recently discovered field-free SOT mechanisms, respectively. A cross-layer analysis is presented involving device modeling, circuit-level optimization, and architecture-level evaluation. First, the principle of the magnetization switching is analyzed with the macrospin simulation. Then, the optimization strategies at the circuit level are generalized through the SPICE-type simulation. Finally, we build up the memory architecture with the SOT-MRAMs, STT-MRAM, and static RAM. Their read/write performances are evaluated with NVSim software. It is demonstrated that one of the studied SOT-MRAMs shows the promising prospect in the non-volatile memory, especially suitable for high-capacity cache. [ABSTRACT FROM AUTHOR]

The conductivity of spin field-effect transistor (spin-FET) can be modulated by controlling the spin degree of freedom; therefore, emerging low-power applications can be explored. In this paper, we propose a novel device called multi-gate spin-FET where multi-gate voltages can successively modulate the spin of the electrons. Various logic functions can be implemented with multi-gate spin-FET by setting the appropriate channel lengths. First, we present an electrical model of the multi-gate spin-FET which considers the physical mechanisms and the fitting of experimental results. The availability of the electrical model is validated by the dc simulation. Afterward, typical logic circuits are designed with the multi-gate spin-FET, including NAND gate, XOR gate, full adder, and a representative three-input logic gate. Transient simulation results validate the functional behaviors of these logic circuits. Finally, based on an analysis of power consumption, we conclude that the multi-gate spin-FET is a more energy-efficient device compared with the conventional CMOS FET. [ABSTRACT FROM AUTHOR]

Magnetic random access memory (MRAM) is experimentally proved intrinsically immune to radiation effects including heavy-ion irradiation and total ion dose as the data are represented by the spin instead of charges. Hence, it is considered as a promising candidate for aerospace and avionic electronics. However, its CMOS peripheral read/write circuits are much more vulnerable to radiation-induced single-event upset (SEU) and double-node upset (DNU) induced by charge sharing. This paper presents a novel radiation-hardening design of the peripheral circuitry for spin orbit torque (SOT)-MRAM to address abovementioned issues effectively. Transient simulations are performed based on a physics-based SOT-magnetic tunnel junction compact model and a 65 nm CMOS design kit. Simulation results validate that the proposed hardening read/write circuits are strongly robust against SEUs and DNUs. Furthermore, the proposed hardening read circuit shows the improvement of hardware area and reliability compared with the previous works. [ABSTRACT FROM AUTHOR]

Spintronics-based devices and circuits attract massive research interest from both academia and industry. A number of the devices and logic circuits have been proposed such as spin-based magnetic tunnel junction and all spin logic gate. A fundamental spin-based device, spin field-effect transistor (spin-FET) is one of the most interesting spin-based devices to address the power issue of semiconductor transistors which is still a research focus. In this paper, we first present an electrical model for the spin-FET based on both theoretical and experimental results. The theories of spin injection and detection are considered by a current driver of the spin-FET. Gate voltage modulation following Datta–Das theory is combined with the experimental results from several works of literature. Afterward, through the dc analysis of two spin-FETs with different channel materials, we demonstrate that the channel using InAs is a better choice to make a feasible spin-FET. The channel length is also optimized by the comparison of simulation results. Finally, a local geometry spin-FET model suitable for logic design is implemented with Verilog-A language and integrated on Cadence platform. Using our model, a low-power inverter is designed based on the concept of complementary spin-FET, and a logic circuit is proposed to implement AND and NOR logic functions. Simulation results validate the behaviors of the logic circuits and availability of our model. [ABSTRACT FROM AUTHOR]

Perpendicular-anisotropy magnetic tunnel junction (MTJ) is one of the most promising candidates to build hybrid logic-in-memory architecture, because of its nonvolatility, infinite endurance, and 3-D integration with a CMOS technology. A novel magnetic full-adder (MFA) based on this architecture is proposed, with MTJs switched by spin-Hall-assisted spin-transfer torque (STT). Owing to the assistance of spin-Hall effect (SHE), MTJ switching time can significantly be reduced, and high operation frequency can be achieved. Moreover, the endurance of oxide barrier is largely enhanced as the requirement of lower write voltage. Using an industrial CMOS 28 nm design kit and a physics-based three-terminal spin-Hall-assisted STT-MTJ model, functionality and performance of the proposed MFA have been simulated and validated. A 1 ns STT current pulse assisted by 0.35 ns SHE current pulse is sufficient to switch the MTJ configuration. When compared with the previous MFAs based on STT-MTJ, the proposed MFA achieves 38% less operation time and 31% less power consumption to perform read and write operations. [ABSTRACT FROM AUTHOR]

Thanks to the progress in nonvolatile (NV) devices, such as magnetic tunnel junctions and phase change memories, various NV logic blocks have recently been proposed to overcome energy/delay bottlenecks caused by von Neumann computing architecture. The ferroelectric tunnel memristor (FTM) is an emerging NV multilevel device and was recently reported to show excellent performance. In this paper, we demonstrated that the short-circuit effect in an FTM provides the opportunity to design a novel FTM-based Boolean logic block. This block is composed of an FTM and a load resistor. Unlike classical schemes, where at least two cells are required as operands, our FTM-based block implements logic operation inside a single memristor. With a compact model of an FTM, transient simulation is performed to validate NAND and NOR logic functions. Finally, we provide the method of performance optimization and discuss the advantages/disadvantages of the proposed logic block to summarize our work. [ABSTRACT FROM AUTHOR]

Spin-transfer torque magnetic random access memory (STT-MRAM) offers nonvolatility, good scalability, high speed, and low-power benefits. Multilevel cell (MLC) is an efficient technology to boost the storage density of the STT-MRAM. However, the conventional MLC structure is not suitable for more than 2-b storage due to inefficient multistep read/write operations. In this article, combining the emerging spin-orbit torque (SOT) and STT mechanisms, we propose a novel STT/SOT hybrid triple-level cell (TLC) MRAM cell structure. Corresponding write and read schemes are designed for this hybrid bit-cell to achieve low-cost operations. Unlike the regular stacked TLC, 3-b data can be written in two steps in the proposed cell structure, and be read in parallel with the assistance of SOT. Simulation results show that the proposed structure achieves 32% and 43% savings on write delay and energy consumption, respectively. Monte Carlo statistic simulation results indicate 1.4 × improvement in sensing margin as well. [ABSTRACT FROM AUTHOR]

In the current big data era, the memory wall issue between the processor and the memory becomes one of the most critical bottlenecks for conventional Von-Newman computer architecture. In-memory processing (IMP) or near-memory processing (NMP) paradigms have been proposed to address this problem by adding a small amount of processing units inside/near the memory. Unfortunately, although intensively studied, prior IMP/NMP platforms are practically unsuccessful because of the fabrication complexity and cost efficiency by integrating the processing units and memory on the same chip. Recently, emerging nonvolatile memories provide new possibility for efficiently implementing the IMP/NMP paradigm. In this paper, we propose a cost-efficient IMP/NMP solution in spin-transfer torque magnetic random access memory (STT–MRAM) without adding any processing units on the memory chip. The key idea behind the proposed IMP/NMP solution is to exploit the peripheral circuitry already existing inside memory (or with minimal changes) to perform bitwise logic operations. Such an IMP/NMP platform enables rather fast logic operations as the logic results can be obtained immediately through just a memory-like readout operation. Memory read and logics not, and/nand, and or/nor operations can be achieved and dynamically configured within the same STT–MRAM chip. Functionality and performance are evaluated with hybrid simulations under the 40 nm technology node. [ABSTRACT FROM AUTHOR]

With the rapid increase of leakage currents, non-volatile memories have become competitive candidates in the next-generation computer architecture. Among them, STT-MRAM shows great promise in working memory with high density, high speed and tremendous endurance, etc. However, based on our investigations, the dynamic write power and read reliability are two critical challenges of STT-MRAM. In this work, we propose a synergistic pseudo-differential sensing (PDS) framework that employs device, circuit and architectural techniques to address these challenges. In specific, three design techniques, including cell cluster, asymmetric sensing amplifier and self-error-detection-correction, are proposed to implement the PDS framework. We show that the holistic device-circuit-architecture cross-layer co-design enables STT-MRAM to be utilized in the cache memory, benefiting from the improved density, reliability and energy-efficiency. Our experimental results show that the proposed PDS scheme improves the read margin by ∼35.6 percent, reduces the area, read latency, read energy, write latency and write power by ∼46.7, ∼9.8, ∼30.3, ∼2.3 and ∼31.1 percent respectively, compared with the typical 1T1MTJ cell structure for the cache capacity of 8 MB. In addition, the proposed PDS scheme reduces the dynamic energy by ∼32.9 percent and leakage energy by ∼830 percent, improves the IPC by ∼1.3 percent and miss rate by ∼36.9 percent respectively, compared with conventional SRAM based cache. [ABSTRACT FROM AUTHOR]

Spin-transfer torque magnetic random access memory (STT-MRAM) has emerged as a promising candidate for the next-generation high-speed, low-power, and scalable nonvolatile memory technology. Its advantageous features have attracted much attention in the area of research and development, and a number of preindustrial prototypes and small-scale products have been demonstrated. One expects to widely commercialize it in the next few years. One of the critical issues that blocks STT-MRAM’s wide commercialization is its low sensing reliability due to the relatively small tunnel magnetoresistance ratio of the magnetic tunnel junction (MTJ) and the continuously increasing process variations, especially as technology process scales down to the deep submicrometer nodes (e.g., 40 nm). In this paper, we present a variation-tolerant high-reliability sensing circuit for deep submicrometer STT-MRAM. This circuit, using triple-stage sensing and charge transfer amplification, is able to tolerate significantly the process variations and improve greatly the sensing margin by sacrificing some sensing time. Using a CMOS 40 nm design kit and a precise STT-MTJ compact model, transient and Monte Carlo simulations have been carried out to demonstrate its sensing performance. [ABSTRACT FROM AUTHOR]

Spin transfer torque-based magnetic random access memory (STT-MRAM) is considered as one of the most promising candidates for the next generation of nonvolatile memories; however, its storage density and reliability are currently uncompetitive compared with other nonvolatile memories (e.g., NAND flash). In this paper, a dual-functional memory cell structure, named DFSTT-MRAM, is proposed by stacking multiple magnetic tunnel junctions (MTJs) on top of the CMOS access transistor. In such a structure, the cell can be dynamically configured between two possible functional modes, i.e., high-reliability mode (HR-mode) and multilevel cell mode (MLC-mode), based on the data requirements of the addressed applications. The DFSTT-MRAM cell was electrically modeled based on the perpendicular magnetic anisotropy CoFeB/MgO/CoFeB MTJ integrating the STT stochastic switching behaviors. Transient and Monte Carlo simulations were then performed to evaluate its MLC functionality and reliability performance. Our evaluation results show that the DFSTT-MRAM cell can indeed realize MLC capability providing proper write/read control at the MLC-mode and enhance the intrinsic cell reliability by several orders of magnitude when operating at the HR-mode. This cell structure provides a flexible memory cell design for future advanced applications, such as high-density nonvolatile memory and neuromorphic circuits. [ABSTRACT FROM AUTHOR]

With the process node further scaling down, the bit cell of magnetic random access memory (MRAM) device suffers from severe failure and reliability problems due to its process variation. In this article, we explored the variability of a promising toggle spin torques MRAM (TST-MRAM) in detail, which achieves ultrafast switching speed and high endurance and is expected to be applied as upper-level caches. Our research is conducted with a 14 nm FinFET design kit, the basic performance of TST-MRAM and different pulse conditions are explored, and then the variation effect of device parameters is discussed and compared in detail as well as the write error rate (WER) under different voltages. The results demonstrate that the variation of access transistors dominates the variability, where the transistor in the spin–orbit torque (SOT) branch has a greater negative impact than the transistor in the spin transfer torque (STT) branch. To further reduce WER, a better structure with diodes of bit cell is proposed. [ABSTRACT FROM AUTHOR]

As the speed gap of the modern processor and the off-chip main memory enlarges, on-chip cache capacity increases to sustain the performance scaling. As a result, the cache power occupies a large portion of the total power budget. Spin transfer torque magnetic memory (STT-MRAM) is proposed as a promising solution for the low power cache design due to its high integration density and ultralow leakage power. Nevertheless, the high write power and latency of STT-MRAM become new barriers for the commercialization of this emerging technology. In this paper, we investigate the thermal effect on the access performance of STT-MRAM, and observe that the temperature can affect the write delay and energy significantly. Then, we explore the nonuniform cache access (NUCA) design of the chip-multiprocessors with STT-MRAM-based last level cache (LLC). A thermal aware data migration policy, called “Thermosiphon,” which takes advantage of the thermal property of STT-MRAM, is proposed to reduce the LLC write energy. This policy splits the LLC into different regions dynamically based on the thermal distribution monitored by thermal sensors available on-chip, and adaptively migrates write intensive data among different thermal regions considering the thermal gradient. Compared to the conventional NUCA design, our proposed design can save 41.2% write energy at most and 13.01% on average with negligible hardware overhead. [ABSTRACT FROM AUTHOR]

Circuit obfuscation is a frequently used approach to conceal logic functionalities in order to prevent reverse engineering attacks on fabricated chips. Efficient obfuscation implementations are expected with lower design complexity and overhead but higher attack difficulties. In this paper, an emerging obfuscation approach is proposed by leveraging spin-orbit torque (SOT) devices-based look-up-tables as reconfigurable logic to replace the carefully selected gates. It is essentially impossible to identify the obfuscated gate with SOTs inside according to the physical geometry characteristics because the configured functionalities are represented by magnetization states. Such an obfuscation approach makes the circuit security further improved with high exponential attack complexities. Experiments on MCNC and ISCAS 85/89 benchmark suits show that the proposed approach could reduce the area overheads due to obfuscation by 10% averagely. [ABSTRACT FROM AUTHOR]