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In this paper, we describe an improved SPICE model for the negative capacitance field-effect transistor (NCFET). According to the law of conservation of charge, the model is built based on the relationship between the gate charge of the MOSFET and the charge reserved by the ferroelectric layer and includes the parasitic resistance and capacitance into consideration. Based on the model, the drain-induced barrier lowering (DIBL) and the negative resistance (NR) of the NCFET are analyzed. Finally, taking two well-known analog blocks (the current mirror and the latch comparator) for example, impacts of the DIBL effect and the NR property on analog circuit performances are discussed. Thanks to utilization of the NR feature, not only can impacts of the DIBL effect and the channel-length modulation (CLM) effect be alleviated to improve the mirroring accuracy, but also the comparison speed of the latch comparator be accelerated. [ABSTRACT FROM AUTHOR]

Charge scaling data converters include a binary-weighted capacitor array in their structure. New methods for the placement and sizing of capacitor arrays with increased ratio accuracy and improved converter linearity are presented in this paper. A new model of statistical variation is used, which takes into account both spatial correlation between devices and device area. This is combined with a novel analytical model for the linearity metrics of a charge scaling digital-to-analog converter. Minimizing the variance of the linearity metrics directs a new chessboard placement method for the capacitor array. Chessboard placement is shown to be superior to the state of the art in consideration of both random and systematic mismatch. The new analytical model is then used to develop a flow for capacitor array sizing. [ABSTRACT FROM PUBLISHER]

The propagation of Analog Single Event Transients (ASETs) to multiple outputs of Bipolar Junction Transistor (BJTs) Integrated Circuits (ICs) is reported for the first time. The results demonstrate that ASETs can appear at several outputs of a BJT amplifier or comparator as a result of a single ion or single laser pulse strike at a single physical location on the chip of a large-scale integrated BJT analog circuit. This is independent of interconnect cross-talk or charge-sharing effects. Laser experiments, together with SPICE simulations and analysis of the ASET’s propagation in the s-domain are used to explain how multiple-output transients (MOTs) are generated and propagate in the device. This study demonstrates that both the charge collection associated with an ASET and the ASET’s shape, commonly used to characterize the propagation of SETs in devices and systems, are unable to explain quantitatively how MOTs propagate through an integrated analog circuit. The analysis methodology adopted here involves combining the Fourier transform of the propagating signal and the current-source transfer function in the s-domain. This approach reveals the mechanisms involved in the transient signal propagation from its point of generation to one or more outputs without the signal following a continuous interconnect path. [ABSTRACT FROM PUBLISHER]

This paper presents a comprehensive investigation of several important error sources for the successive-approximation register (SAR) analog-to-digital converters (ADCs). The error sources that we discuss in this paper include the dynamic comparator offset, the dynamic gain error of digital-to-analog converter (DAC), the capacitor mismatch of capacitive DAC, the incomplete settling of DAC, the undershoot of reference voltage, and the input signal coupling. The integral/differential nonlinearities (INL/DNL) of SAR ADCs that are resulted from these error sources are analyzed and addressed. A diagnostic procedure is presented to identify the possible error sources based on the INL/DNL plots. In addition, design suggestions for overcoming these problems are also offered and recommended in this paper. [ABSTRACT FROM AUTHOR]

A new current-comparator-based dual-channel calibration system for AC currents and AC voltages in the millivolt range has been developed. The range of generated currents is 1 mA–5 A, and the range of generated voltages is 1–500 mV. The calibration system in-phase and quadrature expanded measurement uncertainties ( $k=2$ ) are within 25\cdot 10^{\mathrm {\mathbf {-6}}} . Although the system has been developed primarily for operation at power frequencies, it is also capable of operating at frequencies up to 1000 Hz with slightly increased uncertainties. The traceability to SI units is established through the calibration of AC voltage by means of AC/DC transfer and DC voltage reference, standard resistor, capacitor, and current comparator ratios. [ABSTRACT FROM PUBLISHER]

This paper presents the design and implementation of a rail-to-rail 460-kS/s 10-bit successive approximation register analog-to-digital converter (ADC) for the power-efficient capacitance measurement. The specifications of ADC are optimized at system level, emphasizing the ADC following a switched-capacitor capacitance-to-voltage (C2V) converter. To be compatible to the output of C2V, a bootstrap switch with body effect reduction is adopted to provide the rail-to-rail processing ability. The charge redistribution converter is implemented by a single-ended cascaded binary-weighted capacitive digital-to-analog converter (DAC). The total area of the DAC array is not only limited by the matching behavior but also by the noise performance of C2V. To relax the settling requirement and improve the power efficiency, self-timing technique is employed which borrows extra half clock period for open-loop settling of preamps. The balance between noise and power consumption of dynamic comparator with preamps is also considered. The ADC circuit was implemented in 0.18- \mu m CMOS technology and occupies an active area of 0.18 \mathrm{mm}^{2} . The tested prototype achieves a signal-to-noise-plus-distortion ratio of 54 dB and a spurious-free dynamic range of 68 dB. The integral nonlinearity and differential nonlinearity are 0.5 and 0.34 least-significant-bit, respectively. The total power consumption is 21 \mu $ W corresponding to 110 fJ/conversion-step figure of merit. [ABSTRACT FROM PUBLISHER]

This paper presents two circuits that allow us to accurately detect either the inductor current zero crossing, or the continuous/discontinous conduction modes boundary in the switched-mode dc-dc converters. Achieved detection accuracy allows us to improve the control and efficiency of the integrated high-output current converters, i.e., converters with low-resistance power switches. Detection is based on the voltage zero-cross detector, which provides ideally zero input-referred offset and very fast results. The concept of voltage polarity detector is based on the association of a dynamic current mirror and a simple autozero comparator. This paper describes the main concept of both circuits, aspects of the design allowing us to achieve high accuracy, and presents obtained results. Circuits' performances are demonstrated on the integrated step-down dc-dc converter with IOUT = 2.5 A 30-mΩ NMOS power stage. Measured accuracy of the detection is in order of <;15 mA. [ABSTRACT FROM AUTHOR]

An improved power standard derived from a current comparator power bridge for calibrating active/reactive power and energy meters under sinusoidal conditions is described. Measurements can be made at any power factor from zero lag through unity to zero lead, at positive or negative power, at 120 V, 5 A, and 50 or 60 Hz. The improved power standard has an estimated uncertainty of not more than 2.5 \mu\W/VA at k = 1. Special high-accuracy current and voltage range extenders have been incorporated to extend the current and voltage ranges up to 200 A and 1200 V, respectively. [ABSTRACT FROM PUBLISHER]

The Korea Research Institute of Standards and Science (KRISS) has established a reference 400-kV capacitive voltage divider for the purpose of calibrating industrial high-voltage measuring systems on site. In order to confirm the performance characteristics of the divider, a comparison of the calibration systems between KRISS and National Research Council Canada with the divider used as the transfer standard was conducted. This paper presents the comparison results and its analysis in obtaining the voltage-dependent performance characteristics of the reference 400-kV voltage divider over its entire range. [ABSTRACT FROM AUTHOR]

A modified technique for calibrating both the capacitance-ratio and dissipation-factor (DF) dials of a current-comparator-based high-voltage capacitance bridge has been developed at the Korea Research Institute of Standards and Science (KRISS). The capacitance-ratio and DF dials are calibrated in the ratio range from 1/1 to 1000/1 and in the DF range from 10 \times 10^-6 to 1 \times 10^-1 for both positive and negative polarities. From the calculated and measured values of the corresponding dial balanced readings, the errors in the capacitance-ratio- and DF-dial readings are derived. The relative uncertainty of the modified calibration technique is also obtained to be not more than 10 \times 10^-6 of unity for the ratio-dial calibration, whereas the relative uncertainty of the DF dials from 1 \times 10^-3 to 1 \times 10^-1 is not more than 0.4% of the dial indication except the dissipation lower than 1 \times 10^-3 for which the corresponding absolute uncertainty is 5 \times 10^-6. The comparison results of the calibration performed at KRISS and the National Research Council of Canada show a good consistency with the measurement uncertainty. [ABSTRACT FROM AUTHOR]

A method for improving the sensitivity (or speed) of a master–slave emitter-coupled logic comparator using emitter degeneration resistors is presented. The degeneration resistors in the latching pair reduce the transistor charging time, thus allowing more time for regeneration. Improved and standard comparators were implemented using the InP/GaInAs heterojunction bipolar transistor technology and were tested at a clock rate of 20 GHz. The improved comparator exhibited better sensitivity (by a factor of 1.7) compared to the standard design. A record low-sensitivity value of 10 mV was obtained. [ABSTRACT FROM AUTHOR]

A radiation-hardened-by-design (RHBD) technique is described for reducing errors due to single-event effects at the floating input nodes of a switched-capacitor comparator. The technique is shown to significantly outperform the alternative ldquobrute forcerdquo design choice of increasing capacitor size. [ABSTRACT FROM PUBLISHER]