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Three-level neutral-point-clamped (3L-NPC) voltage source inverters are widely used in many low- and medium-power applications. However, the 3L-NPC inverter has an inheritance issue of the neutral-point (NP) voltage unbalancing due to the deviation of dc-link capacitor voltages causing distortions for the output waveform quality. Generally, discontinuous pulsewidth modulation (DPWM) is used to diminish the stress on power transistors and prolong their lifespan, however; it is not capable of solving the issue of NP voltage unbalancing. Therefore, this article proposes a simple voltage balancing control based on DPWM with a hysteresis NP voltage band. The balancing control method is only activated once the capacitance voltage error exceeds the hysteresis band by generating a momentary offset on the opposite direction of the DPWM offset. In this way, both top and bottom capacitance voltages will converge within a predefined error band. Various hysteresis error bands are investigated by analyzing the power losses, total harmonic distortions, and common mode voltage. The advantages of this proposed method are its simplicity and ease of control while maintaining the features of DPWM. The effectiveness of the proposed method is validated using simulation and experimental results. [ABSTRACT FROM AUTHOR]

Switched-capacitor-based multilevel inverters have been gaining increasing attention in recent years in view of their voltage-boosting capability and capacitor self-balancing properties. However, the existing topologies, which comprise frontend switched-capacitor cells and a backend H-bridge, result in longer discharging duration in some of their switched-capacitors. In addition, the adoption of backend H-bridge introduces common-mode voltage and necessitates multiple dc sources for voltage level extension. To resolve these problems, this article proposes a novel topology comprises a T-type inverter and n cascaded switched-capacitor cells. It requires only a single dc source and it manages to mitigate the common-mode voltage by connecting the neutral of ac output to the mid-point of dc link. All switched-capacitors in the proposed topology are ensured to be charged for at least half of the fundamental period to alleviate the capacitor voltage ripples and current spikes. The operation of the proposed topology is analyzed and experimental results are presented for validation. [ABSTRACT FROM AUTHOR]

The integration of switched-capacitor techniques into multilevel inverters (MLIs) with a dc source string contributes to the boosting of voltage gain, renders it particularly attractive in reducing the number of input dc sources in the series string. However, the recent two-stage MLI topologies suffer from high voltage stress across the backend H-bridge. Addressing this concern, an improved topology, namely the one-switched-capacitor integrated MLI (1SCI-MLI) is proposed in this paper. An extended topology of 1SC-MLI is also established by appropriate incorporation of another switched-capacitor circuit. The two proposed topologies are endowed with voltage boosting capability. They also feature low switch count and low number of dc sources. More importantly, they resolve the high voltage stress problem in the existing counterparts. Their corresponding operational analysis and comparisons with recent MLI topologies are discussed. Simulation and experimental results from a laboratory prototype are presented to validate the effectiveness of the proposed topologies. [ABSTRACT FROM AUTHOR]

The conventional three-level active-neutral-point-clamped (ANPC) inverter requires high dc-link voltage at least twice the peak of ac output. To reduce the dc-link voltage, a recent topology that enhanced the voltage gain from half to unity has been presented. In this letter, an alternative ANPC topology is established by using two T-type inverters. Two floating capacitors with self-voltage balancing capability are integrated to achieve a voltage-boosting gain of 1.5. In addition, the proposed topology is capable of generating seven voltage levels. Its operation is validated through circuit analysis followed by experimental results of a prototype. [ABSTRACT FROM AUTHOR]

This paper proposes the new clamping angle control (CAC) pulse width modulation (PWM) method to restore its maximum linear modulation range of voltage source inverters (VSIs) reduced by the duty ratio limitation in hardware implementation, which makes the VSIs to operate nonlinearly in the high modulation range. The deadtime and the bootstrap gate driver circuit mainly cause this duty ratio limitation in practice. In particular, the bootstrap gate driver circuit is used in many industrial applications by avoiding the additional power supply to apply the gate-source voltage of power switches, and therefore making the VSIs to be small size with the low cost. First, the proposed CACPWM method is theoretically analyzed. Then, it is applied in the high modulation range to overcome the limitation of the duty ratio due to the use of the bootstrap gate driver circuit. Thereafter, its practical effectiveness is verified by both simulation and experimental tests. Also, the resulting harmonic distortions are compared with those by the conventional PWM methods. [ABSTRACT FROM AUTHOR]

The purpose of neutral-point voltage balancing algorithms in the three-level neutral-point clamped (3L-NPC) topology is to eliminate the voltage unbalance of top- and bottom-side dc-link voltages (neutral-point voltage). These algorithms are divided into dc unbalance and ac unbalance compensation methods. The dc unbalance causes distortion of output currents; therefore, this problem has to be solved. The ac unbalance implies that there is an ac ripple in the top- and bottom-side dc-link voltages. In applications using 3L-NPC topology, a large dc-link capacitor value is required to mitigate this ac unbalance problem. As a result, the size and the cost of applications become large and expensive. In this paper, a compensation method for mitigating the ac unbalance of the neutral-point voltage is proposed, which causes the dc-link capacitor value to be small, when a carrier-based pulse width modulation method is applied. The proposed method compensates the ac unbalance of the neutral-point voltage by adding an optimal compensation value to the reference duty signals. This compensation value is calculated simply by currents and reference duty signals. The calculation process of the optimal compensation value is discussed, and the effectiveness of the proposed method is verified with simulations and experiments. [ABSTRACT FROM PUBLISHER]

Three-level topologies are widely used in back-to-back converters of wind turbine generation (WTG) systems. In comparison with a conventional two-level topology, three-level topologies have more advantages, particularly for the high power. Neutral-point clamped (NPC) and T-type are typical three-level topologies. An open-switch fault of a three-level rectifier that is connected to a permanent-magnet synchronous generator (PMSG) leads to the current distortion and torque vibration in WTG systems. Furthermore, WTG systems can break down in the worst case. Therefore, a tolerance control for open-switch faults is required to improve the reliability of WTG systems. WTG systems by applying the tolerance control can be stopped safely and prevent additional problems. Depending on the situation, it can keep the operation of WTG systems under open-switch fault. The effects of outer open-switch faults of three-level rectifiers are analyzed by considering PMSG specifications in this paper. Moreover, a tolerance control for outer open-switch faults of the NPC and T-type three-level rectifiers are proposed with existing tolerance controls for inner open-switch faults. The proposed tolerance control is to inject the exact $d$-axis current value to eliminate current distortion. The simulation and experiment are conducted to prove the feasibility of the proposed tolerance control and to identify its performance. [ABSTRACT FROM PUBLISHER]

In wind turbine generation (WTG) systems, a back-to-back converter with a neutral-point-clamped (NPC) topology is widely used because this topology has more advantages than a conventional two-level topology, particularly when operating at high power. There are 12 switches in the NPC topology. An open-switch fault in the NPC rectifier of the back-to-back converter leads to the distortion of the input current and torque vibration in the system. Additionally, an open-switch fault in the NPC inverter of the back-to-back converter causes the distortion of the output current. Furthermore, the WTG system can break down in the worst case scenario. To improve the reliability of WTG systems, an open-switch fault detection method for back-to-back converters using the NPC topology is required. This study analyzes effects of inner and outer open-switch faults of the NPC rectifier and inverter and describes a novel open-switch fault detection method for all possible open-switch faults in the back-to-back converter. [ABSTRACT FROM AUTHOR]

Multilevel converter topologies are widely used in applications of wide-power range. The T-type topology, which is one of many three-level topologies, has an advantage in terms of efficiency compared to the neutral-point-clamped (NPC) type. In applications using the T-type topology, interest in reliability has been increased recently. Therefore, the open-switch fault detection method and tolerance control for T-type rectifiers, which are different from those of T-type inverters, are necessary to improve the reliability of applications. When the open-switch fault of switches connected to a neutral point occurs, an NPC-type rectifier cannot restore distorted input currents; however, a T-type rectifier is able to eliminate input current distortion completely. In this paper, an open-switch fault detection method is proposed and can find a position of the open-switch fault. Moreover, two tolerance controls based on space vector modulation are proposed and their characteristics are analyzed. The effectiveness and performance of the proposed open-switch fault detection method and two tolerance controls are verified by simulations and experiments. [ABSTRACT FROM PUBLISHER]

Open- and short-circuit faults are the most severe issues that affect the stability and reliability of power conversion systems. The space vector modulation (SVM) technique is widely used to control power converters. However, conventional SVM is incapable of controlling the system effectively when such faults occur. Considering these, this article proposes a modified SVM that is capable of tolerating the extreme cases of faults (including multi open-/short-circuit faults) simultaneously. An innovative fault tolerance method is proposed to tolerate multifaults in hybrid active neutral point converters (HANPCs). Furthermore, new voltage reference signals are created in addition to calculating voltage offset and inserting modified switching sequences. A descriptive performance analysis of the modified SVM technique is applied under healthy and faulty conditions. Correspondingly, the effects of the total harmonic distortion of the system performance are also highlighted and explained. The results reveal that the proposed control strategy can effectively maintain healthy and safe operation under faulty conditions without the need for additional parts or alteration of the topology configuration. In addition, the proposed method can be applied to HANPCs without special requirements to withstand high voltage levels. The effectiveness of the proposed method is verified by simulation and experimental results. [ABSTRACT FROM AUTHOR]

This article proposes a method to eliminate abnormal output voltages generated in three-level hybrid active neutral-point clamped (ANPC) inverters. The hybrid ANPC inverter is a topology in which silicon (Si) devices are replaced with silicon-carbide (SiC) devices in part from the conventional ANPC topology. The hybrid ANPC inverters have the advantages of high switching frequency and low power switching loss due to the SiC devices. In this hybrid ANPC inverter, abnormal output voltages occur when the polarity of the output pole voltage is changed from positive to negative. The cause of the abnormal voltages is the switching time difference between the Si and SiC devices, and it is various from a few nanoseconds to a few microseconds. These abnormal output voltages need to be eliminated as it leads to degraded output power quality in the hybrid ANPC inverters. The proposed switching method effectively eliminates the abnormal output voltages and reduces output current distortion. The performance of the proposed method is verified using a prototype of the new three-level hybrid ANPC inverter type through both simulations and experiments. [ABSTRACT FROM AUTHOR]

This article presents a dc-link capacitor lifetime improvement method for three-level photovoltaic hybrid active neutral-point clamped inverters in full modulation index range. The capacitors are one of the components with vulnerable reliability in a power conversion system. The dc-link capacitor current ripples lead to temperature rise and wear-out failure of the capacitors. The accumulated thermo-mechanical damages from the temperature rise reduce the capacitor lifetime and reliability of the system. The proposed modulation method suppresses effectively the dc-link capacitor current ripple to improve the capacitor lifetime. In this article, the proposed method is discussed via a comparison with conventional space-vector pulsewidth modulation in full modulation index range. The modulation index range is divided into two regions, namely medium-vector modulation and hybrid modulation region. The capacitor lifetime is evaluated by the capacitor lifetime model according to the modulation methods and modulation regions. The effectiveness of the proposed modulation method is verified through simulation and experimental results. [ABSTRACT FROM AUTHOR]

Conventional active-neutral-point-clamped (ANPC) inverters exhibit low voltage gain that inherently leads to a high dc-link voltage requirement. An improved ANPC inverter that is capable of generating five voltage levels has recently reduced the dc-link voltage twofold to achieve unity gain. This led to the development of a single-stage dc–ac power converter with no frontend boost dc–dc converter. This article proposes novel ANPC inverters capable of unity or boosted voltage gain while generating higher voltage levels. The first topology can provide a voltage gain of 1.5 and extends the number of levels to seven by incorporating only one additional switch. The topology can also be extended by adding three switches and one floating capacitor to generate nine levels with unity voltage gain, or 11 levels with a voltage gain of 2.5. The proposed ANPC inverters and their operations are comprehensively discussed. Experimental results are provided to validate the feasibility of the proposed ANPC inverters. [ABSTRACT FROM AUTHOR]

This paper presents an improved rotating restart method for a sensorless permanent magnet synchronous motor (PMSM) drive system using repetitive zero voltage vectors. To restart the sensorless PMSM drive system, a method for estimating initial rotor position and speed is required due to the absence of sensors such as encoders and resolvers. The rotor position and speed can be estimated using the short-circuit current vectors generated by applying zero voltage vectors. However, the estimated rotor position and speed can be inaccurate. The inaccurate rotor position that causes the current is distorted by the back-electromotive force of the PMSM, and it is impossible to precisely control the system. Therefore, an improved rotating restart method for the sensorless PMSM drive system using repetitive zero voltage vectors is proposed. The effectiveness of the proposed method is verified through simulation and experimental results using a 5-kW PMSM drive system. [ABSTRACT FROM AUTHOR]

This paper proposes advanced speed control for a five-leg voltage source inverter (FLVSI) that drives the dual three-phase induction motor system used in industrial manufacturing processes. The advanced speed control method consists of two controllers: 1) The first is a slip controller that satisfies the application requirement, i.e., to control the mechanical speed of two motors equally regardless of the load condition. 2) The second is an angle controller that satisfies the FLVSI requirement, i.e., to control the phase angle difference between the two motors for minimizing the common leg current because the common leg current can be twice higher than other leg's current depending on the operation condition of the dual motor. Stability analysis of the two controllers under advanced speed control is implemented, and the whole performance of the advanced speed control for the FLVSI-fed dual-motor drive system is shown to identify its feasibility through the experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes a deadbeat finite set model predictive current control based on discrete space vector modulation (DSVM) in order to achieve robust characteristics from the grid impedance variation while guaranteeing high performance of output current waveforms and a fixed switching frequency. The proposed DSVM strategy enables to obtain a large number of virtual voltage vectors without complex initialization process or lookup table, which are the drawbacks of the conventional DSVM strategies. A deadbeat technique was adopted to minimize the number of candidate voltage vectors considered in the cost function in order to avoid the high computational burden caused by considering all voltage vectors. The simulation and experimental results were presented to verify the effectiveness and performance of the proposed method using a two-level grid-connected voltage source inverter. [ABSTRACT FROM AUTHOR]

This paper proposes a novel discontinuous pulse-width modulation (DPWM) method to reduce the current harmonics and improve the system efficiency for a single-phase three-level neutral-point clamped inverter. In single-phase inverters, the unipolar pulse-width modulation (UP-PWM) method is commonly used. However, this method has the disadvantage of power losses due to numerous switching operations. Conventional DPWM methods reduce the power losses and improve efficiency but increase the current total harmonic distortion (THD). To overcome these weaknesses, this paper proposes a hybrid DPWM switching method combining two PWM methods: the UP-PWM method and the conventional DPWM method called one-pole clamped PWM method. Since the proposed DPWM method offers all the advantages of both PWM methods, the optimal performance—with regard to the power losses and current THD—is obtained. The combination of two PWM methods is investigated by analyzing the power losses and current THD. Based on the analysis, the process determining the optimal operating condition is introduced. The effectiveness of the proposed DPWM method is demonstrated through simulations and experiments. [ABSTRACT FROM AUTHOR]

To increase the fault tolerance for cascaded H-bridge multilevel inverters (CHMIs) based on level-shifted pulse width modulation (LS-PWM), a modified LS-PWM method is proposed for the inverters operating under faulty conditions. To cover both open- and short-device fault cases, two types of switching scheme are included in this PWM method. With this PWM method, the neutral shift can be applied as fault-tolerant control for CHMIs based on LS-PWM. Finally, three-phase-balanced line-to-line voltages and currents with minimum harmonic distortion are produced for the inverter with disabled power cells. In addition, this LS-PWM method has the capability to improve power distribution among the H-bridge power cells under the faulty conditions. Simulation and experimental results show that the proposed PWM method performs satisfactorily to achieve fault tolerance. [ABSTRACT FROM AUTHOR]

A new pulsewidth modulation (PWM) strategy which is an alternative approach of the discontinuous PWM (DPWM) for a three-level neutral-point-clamped (NPC) inverter is proposed in this paper. A three-level NPC inverter is completely mature and very well-established topology in high-power applications. However, the three-level NPC inverter has an inheritance problem of the neutral-point voltage unbalancing due to the split dc-link capacitors. This structure can cause large neutral-point voltage ripple. Furthermore, output currents of the three-level NPC inverter are distorted by the neutral-point voltage ripple. Therefore, the neutral-point voltage must be controlled. In this paper, a new DPWM method using two different offsets for the neutral-point ripple reduction is proposed and the effectiveness of the proposed DPWM method is verified by using the simulation and the experimental results. [ABSTRACT FROM PUBLISHER]

The centralized topology with three-level inverters are widely used in photovoltaic (PV) systems due to their less installation costs and complexity. However, the common maximum power point tracking (MPPT) is a disadvantage of the centralized topology particularly under the partial shading and panel mismatch conditions. In this system, if PV modules are separately connected to the split capacitor voltage, the MPPT efficiency can be improved by the proposed control strategy. By the proposed method, the two capacitor voltages can be controlled asymmetrically to perform the separate MPPTs of each PV module connected to separate capacitors. The outputs can be generated without distortion even if two capacitors are asymmetrically regulated. Simulation and experimental results verify the validity and feasibility of the proposed methods. [ABSTRACT FROM PUBLISHER]

This paper proposes a method to reduce the low-frequency neutral-point voltage oscillations. The neutral-point voltage oscillations are considerably reduced by adding a time offset to the three-phase turn-on times. The proper time offset is simply calculated considering the phase currents and dwell time of small- and medium-voltage vectors. However, if the power factor is lower, there is a limitation to eliminate neutral-point oscillations. In this case, the proposed method can be improved by changing the switching sequence properly. Additionally, a method for neutral-point voltage balancing is also proposed. The change in switching frequency by the proposed method and its effects on the outputs are negligible. Simulation and experimental results verify the validity and feasibility of the proposed strategy. [ABSTRACT FROM PUBLISHER]

This paper proposes a new modulation strategy that balances the neutral-point voltage for three-level neutral-clamped inverter systems. The proposed modulation replaces the P-type or N-type small switching states with other switching states that do not affect the neutral-point voltage. The zero and medium switching states are employed to help the neutral-point voltage balancing. This method little bit increases the switching events and output total harmonic distortion. However, this method has a strong balancing ability at all regions. Further, it is very simple to implement in both space vector modulation and carrier-based PWM methods. Simulation and experimental results verify the validity and feasibility of the proposed new modulation strategy [ABSTRACT FROM AUTHOR]

The emerging switched-capacitor-based multilevel inverters offer interesting merits such as self-balancing of capacitor voltages and boosting of voltage gain. While the switched capacitors (SCs) in these topologies are charged in parallel with the dc source, severe current spikes issue is inevitable, rendering them impractical at high power. This article proposes a novel switched-capacitor-based T-type inverter that mitigates the current spikes by enabling soft charging for its integrated SCs, where both SC in the topological structure charges through a dedicated circuit comprises of an inductor and two switches. The proposed topology is capable of five-level ac voltage generation and when compared to a classical T-type/ANPC (active neutral-point-clamped) inverter, it achieves higher dc-link voltage utilization since its maximum attainable voltage gain is doubled. Theoretical findings of the proposed topology are validated by both the simulation and experimental results. [ABSTRACT FROM AUTHOR]

The switched-capacitor-based cascaded multilevel inverters (CMI) have been emerging due to their voltage boosting capability. Unfortunately, they suffer from impulse charging current and nonuniform operation. This article presents a topology termed as dual-T-type five-level CMI to resolve these problems without compromising the desirable voltage boosting characteristic. The main idea is to integrate a half bridge and an inductor to soft charge a capacitor that is connected in series with the dc source. The capacitor enables the voltage gain boosted to two, while the control of eight power switches that constitutes a dual-T structure enables five voltage levels generation. In addition, uniform operation is achieved for cascaded extensions. The operating principle of the proposed topology is analyzed and elaborated. For validation, simulation, and experimental results of a prototype are presented. [ABSTRACT FROM AUTHOR]

This paper proposes a new family of multilevel inverter topology that is able to generate seven voltage levels by utilizing one or two floating capacitors and 10 power switches. This novel boost switched-capacitor seven-level inverter possesses voltage boosting capability with an achievable maximum voltage level 1.5 times the input direct current (dc) voltage. The generation of higher output voltage does not incur high-voltage stress on any power switch in this topology, as the peak inverse voltages of all power switches do not exceed the input source voltage. In addition, capacitor voltage balancing is not essential since the floating capacitors are effectively balanced during the charging and discharging processes. Furthermore, the proposed topology eliminates the need for multiple isolated dc sources, and a single dc source is sufficient in both its single-phase and three-phase topologies. The operating principle and steady-state analysis of the proposed topology are elaborated. Experimental results from a single-phase prototype are then presented to verify the validity of the proposed topology. [ABSTRACT FROM AUTHOR]

This paper analyzes the combination in a cascaded H-bridge multilevel inverter (CHBI) based on transformers with the different turn ratios for increasing the voltage level and proposes the switching method for achieving the output voltage distribution among H-bridge cells (HBCs). The transformers used in this paper are connected to the output of the respective HBCs, and the secondary sides of all the transformers are connected in series for generating the final output voltage. Only one of the transformers, in particular, has a different turn ratio for increasing the output voltage level. In this paper, the possible turn ratio of the special transformer with a different turn ratio is discussed in detail, and a switching method based on the level-shifted switching method for the topology used in this paper is proposed. To verify the effectiveness of the proposed method, a three-phase 21-level CHBI is experimentally tested. [ABSTRACT FROM PUBLISHER]

This paper underpins the principles for generating reactive power in single-phase transformerless photovoltaic (PV) inverters. Two mainstream and widely adopted PV inverters are explored, i.e., H5 and HERIC. With conventional modulation techniques, reactive power cannot be realized in H5 and HERIC due to the absence of freewheeling path in negative power region. Based on the study, modulation techniques are proposed to provide bidirectional current path during freewheeling period. With proposed modulation technique, reactive power control is achieved in H5 and HERIC inverters, without any modification on the converter structures. The performances of the proposed modulation techniques are studied via MATLAB simulation and further validated with experimental results. [ABSTRACT FROM PUBLISHER]

This paper presents an open-circuit fault detection method for a grid-connected neutral-point clamped (NPC) inverter system. Further, a fault-tolerant control method under an open-circuit fault in clamping diodes is proposed. Under the grid-connected condition, it is impossible to identify the location of a faulty switch by the conventional methods which usually use the distortion of outputs because the distortion of the outputs is the same in some fault cases. The proposed fault detection method identifies the location of the faulty switch and the faulty clamping diode of the NPC inverter without any additional hardware or complex calculations. In the case of the clamping diode faults, the NPC inverter can transfer full rated power with sinusoidal currents by the proposed fault-tolerant control. The feasibility of the proposed fault detection and the fault-tolerant control methods for the grid-connected NPC inverter are verified by simulation and experimental results. [ABSTRACT FROM AUTHOR]