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In this paper, it is shown empirically and through simulation that transistor mismatch due to random dopant fluctuation is a function of the well and halo design of the transistor, and that, contrary to conventional expectation, low-threshold transistors can have larger mismatch than higher threshold transistors. The complex dependence of mismatch on well and halo profiles suggests the need for the extension of the conventional Pelgrom approach to characterizing mismatch for a given technology and also suggests means of optimizing mismatch for analog applications. A set of screening criteria for mismatch data analysis are presented to verify that conclusions drawn from the standard deviation of a distribution may be properly applied. [ABSTRACT FROM PUBLISHER]

In contrast to the generally accepted expectation that mismatch is monotonically related to doping level for uniformly doping channels, apparently anomalous results in which short-channel low-doped devices have larger mismatch than higher doped high-threshold devices are shown. However, these results are fully explained and comprehended in the context of device design and random dopant fluctuation, and the correlation of short-channel effect with mismatch suggests yet another manner in which fully depleted undoped-body devices will offer better variation than classic scaled dopant-driven transistors, addressing a critical problem in new technology directions. [ABSTRACT FROM PUBLISHER]

This correspondence briefly describes and reconciles two separate streams of work, which extend the Pelgrom model for a transistor mismatch. While independently conceived and pursued, similar and complementary conclusions have been reported by these groups, refining the understanding of a transistor mismatch to encompass halo-dominated transistor designs. [ABSTRACT FROM AUTHOR]

Vertically stacked junctionless accumulation mode (JLAM) nanowire field effect transistors (NWFETs) outperform inversion-mode (IM) NWFETs below 10-nm technology nodes, but the vertical stacking of nanowires (NWs) has a constraint of position dependent drain current. This paper encompasses: 1) extensive investigation of the impact of series resistance on IM, JL mode, and JLAM NWFET architectures; 2) a proposed approach to mitigate the series resistance; and 3) linearity assessment of stacked JLAM-NWFET for radio frequency (RF) applications. We have suggested that by decreasing the channel doping in the bottom NW with respect to the top NW in a stack, the current can be significantly improved along with the reduction in series resistance. This improves the overall uniformity of drain current in each NW for stacked JLAM-NWFET. The linearity performance of the device is assessed in terms of following figure of merits (FOMs): IIP3, 1-dB compression point, and higher order derivative of transconductance ${g}_{m\textsf {2}}$ and ${g}_{m\textsf {3}}$. These FOMs are evaluated through numerical simulations using Sentaurus Technology Computer-Aided Design to confirm the robustness of the device against intermodulation distortion making it suitable for low power radio frequency integrated circuit design applications. The proposed solution allows higher drive current, improved linearity, and thus lower distortion in stacked JLAM-NWFET. [ABSTRACT FROM AUTHOR]

We examine the impact of line-edge roughness (LER) on the variability in the on-current and saturation threshold voltage of ultrascaled FinFET devices via quantum-mechanical transport simulation. We obtain a realistic model of LER by decomposing the LER into short- $\lambda $ and long- $\lambda $ fluctuations, and we consider their separate influences on device performance. We show that the long- $\lambda $ fluctuations lead to greater device variability than the short- $\lambda $ fluctuations, and we explain the difference between the two cases via the influence of fluctuating quantum confinement arising from the LER. Finally, we consider devices in which the long- $\lambda $ fluctuations of the two fin edges are correlated and demonstrate that this correlation significantly improves the variability. Thus, we show the continued need for fabrication technology either to reduce the amplitude of the long- $\lambda $ fluctuations or to ensure the long- $\lambda $ fluctuations between the sidewalls of ultrascaled FinFET devices are correlated. [ABSTRACT FROM AUTHOR]