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We have interfaced an array of polymer light emitting diodes (OLEDs) fabricated onto a glass substrate to a sheet of paper via a pressure sensitive conducting adhesive. By screen printing a series of capacitive touch pads and connecting tracks onto paper using a low-cost conductive graphite ink, we are able to drive individual pixels in the OLED array via CMOS-based electronics that are also attached to the paper. Three AA batteries are used to power the CMOS electronics, touch pads and the OLED array, with pixels in the array operating at a brightness of up to 210 cd/m2. The work highlights a practical interface between plastic- and paper-based electronics. [ABSTRACT FROM PUBLISHER]

Alternating-aperture phase shift masking (AAPSM), a form of strong resolution enhancement technology, will be used to image critical features on the polysilicon layer at smaller technology nodes. This technology imposes additional constraints on the layouts beyond traditional design rules. Of particular note is the requirement that all critical features be flanked by opposite-phase shifters while the shifters obey minimum width and spacing requirements. A layout is called phase assignable if it satisfies this requirement. Phase conflicts have to be removed to enable the use of AAPSM for layouts that are not phase assignable. Previous work has sought to detect a suitable set of phase conflicts to be removed as well as correct them. This paper has two key contributions: 1) a new computationally efficient approach to detect a minimal set of phase conflicts, which when corrected will produce a phase-assignable layout, and 2) a novel layout modification scheme for correcting these phase conflicts with small layout area increase. Unlike previous formulations of this problem, the proposed solution for the conflict detection problem does not frame it as a graph bipartization problem. Instead, a simpler and more computationally efficient reduction is proposed. This simplification greatly improves the runtime while maintaining the same improvements in the quality of results obtained in Chiang et al. (Proc. DATE, 2005, p. 908). An average runtime speedup of 5.9× is achieved using the new flow. A new layout modification scheme suited for correcting phase conflicts in large standard-cell blocks is also proposed. The experiments show that the percentage area increase for making standard-cell blocks phase assignable ranges from 1.7% to 9.1%. [ABSTRACT FROM AUTHOR]