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This paper deals with a hybrid fault-tolerant converter topology. It is performed through the connection of a classical three-phase three-level neutral-point-clamped (3L-NPC) converter with a fourth three-level flying capacitor (3L-FC) leg. The 3L-FC leg actively balances the 3L-NPC neutral-point voltage. For normal operation mode, this paper proposes a mathematical design of the filter needed to connect these two different topologies. Experimentally, and thanks to the already existing decoupling capacitors of the 3L-NPC converter, this filter requires the addition of only one low size inductance. When one fault of the power switch of the 3L-NPC occurs, this paper proposes a hardware reconfiguration technique based on only two fuses and one thyristor per leg allows a safe postfault operation recovery. This is achieved thanks to a simple fault-detection method and a new technique that combines fault leg isolation and corresponding phase postfault connection to the neutral point. Also, a dedicated field-programmable gate array (FPGA)-based control of the reconfigured converter is synthetized to ensure power system availability under fault operation mode. The converter fault-tolerant capabilities are addressed through simulation results and original overall experimental validations of the fault detection and isolation and the postfault operation steps, carried out on a 15-kW prototype converter. [ABSTRACT FROM AUTHOR]

This paper investigates the field-programmable gate array (FPGA) implementation of a fault-tolerant space vector-hysteresis current control (SV-HCC) for three-phase grid-connected converter. The proposed control ensures continuous operation despite of an open-circuit fault in one grid current measurement circuit (caused by defected cables, lines or connectors at the output of the current measurement circuit). It is based on hardware redundancy of current measurement circuits for fault detection and isolation. The faulty measured current is identified through the computation of residuals with well-defined thresholds. Thanks to the high computation capabilities of FPGAs, the implemented fault-tolerant SV-HCC is executed with a very high sampling frequency and very low execution time. As a consequence, the defined theoretical thresholds remain available for the experimental tests. Several experimental results, carried out on FPGA-based prototyping platform, are given in order to illustrate effectiveness and reliability of the proposed fault-tolerant SV-HCC. [ABSTRACT FROM AUTHOR]

This paper focuses on sensor fault detection and isolation (FDI) for electrical systems. A new, easy and fast FDI algorithm is proposed, keeping system performances unchanged under certain faulty sensor conditions when reconfigurations are available. The proposed FDI algorithm is derived from a parity space approach and is based on temporal redundancies. It is insensitive to parameter variations since no model knowledge is required. Also, it is available for a large class of electrical systems such as single- or three-phase power converters, dc or ac electrical drives, etc. Moreover, the residual threshold used for FDI is accurately defined and is suitable for the whole operating range. Simulations results are presented to illustrate the good functionality of theoretical developments. Numerous experimental results are also shown to validate the effectiveness of the proposed FDI algorithm and to highlight its advantages for the control of electrical systems. [ABSTRACT FROM AUTHOR]