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We fabricate n-channel silicon bulk FinFET with silicon nitride (Si3N4) high- \kappa , silicon nitride/silicon dioxide dual- \kappa , and silicon dioxide (SiO2) low- \kappa spacers, and compare their performance using measurements and TCAD simulations. While all the three devices show similar dc performance, the ac and transient performance of low- \kappa spacer FinFET is better due to lower parasitic capacitance ( {C}_{\mathrm {par}} ). We show that {C} _{\mathrm {par}} in SiO2 spacer FinFET is about half of that with Si3N4 spacer. When the gate length is scaled, the contribution of C \mathrm {par} compared with the intrinsic capacitance ( C \mathrm {ox} ) increases. For FinFET with Si3N4 spacers, C \mathrm {par}/C \mathrm {ox} increases from 36% at 30-nm gate length to 105% when the gate length is scaled to 10 nm, while for FinFET with SiO2 spacers, the ratio changes from 19% to 55% making the latter more suitable for scaling. For SiO2 spacer FinFET, inverter delay is about 13% and 25% lower than Si3N4 spacer FinFET for gate lengths of 30 and 10 nm, respectively. [ABSTRACT FROM PUBLISHER]

Using a self-aligned sidewall microcrystalline-silicon (\muc\-Si) dual channel, comprising a sub-50-nm channel width, a novel 3-D stackable maskless embedded metal-gate thin-film-transistor nanowire device was fabricated on top metal using a tungsten gate-stack and trilayered oxide/nitride/oxide gate dielectric. The results of using a charge-transferring mechanism based on the solution-phased pH of a phosphate buffer solution and vascular endothelial growth factor showed that \muc\-Si surfaces exhibit high potential for use in bioelectronics. The device exhibits long-term reliability regarding bioelectronic probing and is as reliable as the commercially available enzyme-linked immunosorbent assay when conducting a targeted, 100-day therapy for ovarian cancer. Thus, the proposed device exhibits potential for use in label-free, economical, and highly reliable lab-on-chip 3-D applications. [ABSTRACT FROM PUBLISHER]

NBTI trapped charge characteristics and recovery mechanisms are examined by a statistical study of individual trapped charge emissions in nanoscale HfSiON/metal gate pMOSFETs. We measure individual trapped charge emission times in NBTI recovery in a large number of devices. The characteristic time distributions of the first three emitted holes are obtained. The distributions can be well modeled by using a thermally-assisted tunnel (ThAT) detrapping model. NBTI trapped charge energy and spatial distributions and its activation energy distribution in the ThAT model are discussed and extracted. Based on the ThAT model and measured result of single-charge induced Vt shifts, we develop a statistical NBTI recovery \Delta Vt evolution model. Our model can well reproduce the temporal evolutions of a \Delta Vt distribution in a number of NBTI stressed nanometer MOSFETs in relaxation. [ABSTRACT FROM AUTHOR]