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A flip-flop circuit hardened against soft errors is presented in this paper. This design is an improved version of Quatro for further enhanced soft-error resilience by integrating the guard-gate technique. The proposed design, as well as reference Quatro and regular flip-flops, was implemented and manufactured in a 65-nm CMOS bulk technology. Experimental characterization results of their alpha and heavy ions soft-error rates verified the superior hardening performance of the proposed design over the other two circuits. [ABSTRACT FROM AUTHOR]

In this paper, we present D flip-flop, Quatro, and stacked Quarto flip-flop designs fabricated in a commercial 28-nm CMOS FDSOI technology. Stacked-transistor structures are introduced in the stacked Quatro design to protect the sensitive devices of the original structure. Striking either of the stacked devices will not upset the latch because the conduction path to the supply rail is still cut off by the other off-state device. The irradiation experimental results substantiate that the stacked Quatro design has significantly better SEU tolerance (e.g., higher heavy ion upset Linear Energy Transfer threshold and smaller cross-section data) than the reference designs. It introduces power and area penalties because the proposed design duplicates and stacks two sensitive PMOS devices. Additionally, the impact of technology scaling on Quatro in various technology nodes (130-nm, 65-nm, and 40-nm) has been studied suggesting decreasing upset threshold and decreasing cross-section data. [ABSTRACT FROM AUTHOR]

A guard-gate based flip-flop circuit temporally hardened against single-event effects is presented in this paper. Compared to several existed techniques, the organization of components inside the proposed design allows the improved performance– only one $\tau $ (the maximum width of a single-event transient (SET) to tolerate) is added into the setup time. A previously reported low-power delay element is applied, which helps make the proposed design power-efficient. The proposed design was implemented in a 65 nm CMOS bulk technology. Alpha and heavy-ions radiation experiments were performed to characterize its soft-error rates. Experimental results show that the proposed design presents no error with LETs up to 37.3 MeV-cm2/mg. Simulation results from the TFIT further validate the experimental results. [ABSTRACT FROM AUTHOR]