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Collector–emitter voltage (${V}_{\textsf {CE}}$) plateau of the 500-V deep-oxide trench (DOT) silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) during inductive load turn-off is investigated and optimized for the first time in this paper, aiming to reduce the turn-off loss (${E}_{ \mathrm{\scriptscriptstyle OFF}}$). The mechanism of ${V}_{\textsf {CE}}$ plateau is revealed by TCAD simulation. In conventional DOT SOI-LIGBT, the large number of stored carries in the silicon region beneath the DOT (Region I) hinders the extension of depletion layer and slows down ${V}_{\textsf {CE}}$ rising during turn-off, leading to a plateau phase. A novel DOT SOI-LIGBT with dual-controllable vertical field plates (CPFs) is proposed to shorten the ${V}_{\textsf {CE}}$ plateau. The dual CPFs are arranged in the DOT and their electric potentials (${V}_{\textsf {F} 1}$ and ${V}_{\textsf {F} 2}$) are controlled through the connection with scrolled resistive polysilicon filed plate. By adjusting ${V}_{\textsf {F} 1}$ and ${V}_{\textsf {F} 2}$ , the accelerated depletion and extraction of stored carriers in Region I can be realized, resulting in a short ${V}_{\mathbf {CE}}$ plateau duration. The ${V}_{\mathbf {CE}}$ plateau duration can be decreased from 156 ns for the conventional SOI-LIGBT to 60 ns for the proposed SOI-LIGBT with ${V}_{F1} = 0$ V and ${V}_{\textsf {F}2} = {0.5}\,\,{V}_{\textsf {CE}}$. The proposed DOT SOI-LIGBT achieves an ${E}_{ \mathrm{\scriptscriptstyle OFF}} $ 59.2% lower than the conventional DOT SOI-LIGBT at the same ${V}_{ \mathrm{\scriptscriptstyle ON}}$ of 2.96 V. [ABSTRACT FROM AUTHOR]

In this paper, five types of superjunction (SJ) configurations are investigated in the silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT). technology computer aided design simulations are carried out to give insight into the mechanism for improving turn-off loss (${E} _{ \mathrm{\scriptscriptstyle OFF}}$) by adopting SJ in the drift region of SOI-LIGBT. In mechanism revealing, collector–emitter voltage rising during the inductive load turn-off is divided into two phases: slow rising phase (SRP) and rapid rising phase (RRP). It is found that the depletion accompanying with carrier extraction in the drift region and at the collector is responsible for the SRP and RRP, respectively, and accordingly, the difference of turn-off transient among the five types of SJ configurations is clarified. Moreover, reduced ${E} _{ \mathrm{\scriptscriptstyle OFF}}$ can be realized by lowering the transition voltage from SRP to RRP (${V} _{\text {A}}$). Low electric potential from the emitter side can be delivered to the collector side through the undepleted regions in P-pillar, which largely determine ${V} _{\text {A}}$. According to the above-mentioned mechanism, an optimization strategy and a novel SJ SOI-LIGBT with composite P-pillar are proposed for the first time. The proposed SJ SOI-LIGBT achieves an ${E} _{ \mathrm{\scriptscriptstyle OFF}}~76.3$ % lower than the conventional SOI-LIGBT at ON-state voltage drop of ~1.41 V. [ABSTRACT FROM AUTHOR]