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Silicon nanowire (SiNW) field-effect transistors (SiNWFETs) are of great potential as a high-sensitivity charge sensor. The signal-to-noise ratio (SNR) of an SiNWFET sensor is ultimately limited by the intrinsic device noise generated by carrier trapping/detrapping processes at the gate oxide/silicon interface. This carrier trapping/detrapping-induced noise can be significantly reduced by replacing the noisy oxide/silicon interface with a Schottky junction gate (SJG) on the top of the SiNW. In this paper, we present a tri-SJG SiNWFET (Tri-SJGFET) with the SJG formed on both the top surface and the two sidewalls of the SiNW so as to enhance the gate control over the SiNW channel. Both experiment and simulation confirm that the additional sidewall gates in a narrow Tri-SJGFET indeed can confine the conduction path within the bulk of the SiNW channel away from the interfaces and significantly improve the immunity to the traps at the bottom buried oxide/silicon interface. Therefore, the optimal low-frequency noise performance can be achieved without the need for any substrate bias. This new gating structure holds promises for further development of robust SiNWFET-based charge sensors with low noise and low operation voltage. [ABSTRACT FROM AUTHOR]

An experimental study is presented to probe the interface barriers of dopant-segregated silicide–Si diodes with internal photoemission. The spatial information of the interface dipoles, which is believed to be the cause of the effective Schottky barrier height (SBH) modification, is extracted from the field dependence of the barrier heights. A clear difference between the dopant segregation (DS) junctions and a pure Schottky junction is found: Boron DS modifies the effective SBH by forming a \p^+\- \n junction while arsenic DS forms a “Shannon” junction with a fully depleted 1.5-nm doping depth in front of the silicide. [ABSTRACT FROM AUTHOR]