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Transistors have been fabricated with a photoresist mask placed in close proximity to the gate so as to effectively block the angled halo implant from the gate region. Devices for which the halo has been eliminated demonstrate superior drain conductance, while devices with the halo implant show the short-channel effect required for high performance. Asymmetric devices have also been fabricated in a similar manner, producing devices with improved analog characteristics without an additional masking layer. [ABSTRACT FROM AUTHOR]

In contrast to the generally accepted expectation that mismatch is monotonically related to doping level for uniformly doping channels, apparently anomalous results in which short-channel low-doped devices have larger mismatch than higher doped high-threshold devices are shown. However, these results are fully explained and comprehended in the context of device design and random dopant fluctuation, and the correlation of short-channel effect with mismatch suggests yet another manner in which fully depleted undoped-body devices will offer better variation than classic scaled dopant-driven transistors, addressing a critical problem in new technology directions. [ABSTRACT FROM PUBLISHER]

This correspondence briefly describes and reconciles two separate streams of work, which extend the Pelgrom model for a transistor mismatch. While independently conceived and pursued, similar and complementary conclusions have been reported by these groups, refining the understanding of a transistor mismatch to encompass halo-dominated transistor designs. [ABSTRACT FROM AUTHOR]

Application of high-frequency ac stress in the place of conventional dc stress is known to decrease the damage caused by self-heating (SH)-induced hot-carrier injection (HCI) in highly scaled MOSFET devices. However, the effect of hot-carrier degradation on short-channel performance is less explored. In this article, a detailed examination of the drain-induced barrier lowering (DIBL) under hot-carrier stress is presented for 14-nm silicon-on-insulator (SOI) n-channel FinFETs. In particular, the influence of SH-enhanced HCI on DIBL is thoroughly investigated for devices with different geometrical parameters including a number of fins, gate length, and so on at different ac stress frequencies. The change in dominant degrading mechanism from bulk oxide trapping to interface state generation under dc and ac stress is shown to affect DIBL severely. Interestingly, the effect of SH on DIBL is in contrast to that in ON-current degradation. Furthermore, time evolution of DIBL degradation for asynchronous stress waveforms is studied for accurate reliability analysis for short-channel devices. [ABSTRACT FROM AUTHOR]