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Fault-tolerant minimal routing algorithms aim at finding a Manhattan path between the source and destination nodes and route around all faulty nodes. Additionally, some non-faulty nodes that are helpless to make up of a fault-tolerant minimal path should also be routed around. How to label such non-faulty nodes efficiently is a major challenge. State-of-the-art solutions could not address it very well. We propose a path-counter method. It can label every node that are helpless to make up of a fault-tolerant minimal path with low time complexity. By counter the number of fault-tolerant minimal paths, it can: support arbitrary fault distribution, check the existence of fault-tolerant minimal paths, not sacrifice any available fault-tolerant minimal paths. [ABSTRACT FROM AUTHOR]

The movement toward 3D fabrication coupled with Network-on-Chip (NoC) aims to improve area, performance, power, and scalability of many-core systems. However, reliability issue as a perpetual challenge in advanced silicon technology imperils it. Aging is an emerging reliability concern, which degrades the system's performance and causes timing failure eventually. Bias-Temperature-Instability (BTI) and Hot-Carrier-Injection (HCI) are the dominant aging mechanisms, which escalate in high temperature and stress (i.e., usage). In addition to the intra-layer temperature variations, 3D NoCs experience inter-layer temperature variations, which demand necessary investigations for aging as compared to 2D NoC. In this paper, we propose AROMa, an aging-aware deadlock-free adaptive routing algorithm integrated with a novel online aging monitoring system for 3D NoCs. The monitoring system in AROMa exploits Distributed-Centralized-Aging-Table (D-CAT) to obtain routers’ aging rates for each layer of 3D NoCs periodically. Consequently, AROMa swaps between different k-best source-destination shortest paths periodically to avoid highly aged routers, force them in recovery phase of BTI, and accordingly balance aging in the network. We prove that AROMa is deadlock free. Our extensive experimental analysis using gem5 full system mode for PARSEC and SPLASH-2 benchmark suites concludes that AROMa outperforms state-of-the-art works while improving age imbalance by 70 percent and maximum age by 35 percent in 3D NoC with negligible overheads. [ABSTRACT FROM AUTHOR]

Reliability is one of the most challenging problems in the context of three-dimensional network-on-chip (3D NoC) systems. Reliability analysis is prominent for early stages of the manufacturing process in order to prevent costly redesigns of a target system. This article classifies the potential physical faults of a baseline TSV-based 3D NoC architecture by targeting two-dimensional (2D) NoC components and their inter-die connections. In this paper, through-silicon via (TSV) issues, thermal concerns, and single event effect (SEE) are investigated and categorized, in order to propose evaluation metrics for inspecting the resiliency of 3D NoC designs. A reliability analysis for major source of faults is reported in this article separately based on their mean time to failure (MTTF). TSV failure probability induced by inductive and capacitive coupling is also discussed. Finally, the paper provides a formal reliability analysis on the aggregated faults that affect TSV. This formal analysis is critical for estimating the resiliency of different components in order to mitigate the redundancy cost of fault-tolerant design or to examine the efficiency of any proposed fault-tolerant methods for 3D NoC architectures. [ABSTRACT FROM PUBLISHER]

2D-NoCs have been the mainstream approach used to interconnect multi-core systems. 3D-NoCs have emerged to compensate for deficiencies of 2D-NoCs such as long latency and power overhead. A low-latency routing algorithm for 3D-NoC is designed to accommodate high-speed communication between cores. Both simulation and analytical models are applied to estimate the communication latency of NoCs. Generally, simulations are time-consuming and slow down the design process. Analytical models provide, within a fraction of the time, nearly accurate results which can be used by simulation to fine-tune the design. In this paper, a high performance and adaptive routing algorithm has been proposed for partially connected 3D-NoCs. Latency of the routing algorithm under different traffic patterns, different number of elevators and different elevator assignment mechanisms are reported. An analytical model, tailored to the adaptivity of the algorithm and under low traffic scenarios, has been developed and the results have been verified by simulation. According to the results, simulation and analytical results are consistent within a 10 percent margin. [ABSTRACT FROM AUTHOR]

3D ICs can take advantage of a scalable communication platform, commonly referred to as the Networks-on-Chip (NoC). In the basic form of 3D-NoC, all routers are vertically connected. Partially connected 3D-NoC has emerged because of physical limitations of using vertical links. Routing is of great importance in such partially connected architectures. A high-performance, fault-tolerant and adaptive routing strategy with respect to the communication flow among the cores is crucial while freedom from livelock and deadlock has to be guaranteed. In this paper we introduce a new routing algorithm for partially connected 3D-NoCs. The routing algorithm is adaptive and tolerates the faults on vertical links as compared to the predesigned routing algorithms. Our results show a $40-50\%$ improvement in the fraction of intact inter-level communications when the fault tolerant algorithm is used. This routing algorithm is light-weight and has only one virtual channel along the $Y$ dimension. [ABSTRACT FROM AUTHOR]