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The introduction of FinFET architecture was expected to alleviate the issue of mismatch compared with planar technology, given the lower doping levels required. However, several authors have reported better mismatch results for planar technology suggesting additional challenges for FinFET architecture. An additional mechanism previously not considered arising from charge present at points of disturbance in the silicon lattice in tapering and wavering fins is shown to contribute to transistor mismatch. We show that including this mechanism improves the quantitative understanding of mismatch in FinFETs. [ABSTRACT FROM AUTHOR]

In contrast to the generally accepted expectation that mismatch is monotonically related to doping level for uniformly doping channels, apparently anomalous results in which short-channel low-doped devices have larger mismatch than higher doped high-threshold devices are shown. However, these results are fully explained and comprehended in the context of device design and random dopant fluctuation, and the correlation of short-channel effect with mismatch suggests yet another manner in which fully depleted undoped-body devices will offer better variation than classic scaled dopant-driven transistors, addressing a critical problem in new technology directions. [ABSTRACT FROM PUBLISHER]

This correspondence briefly describes and reconciles two separate streams of work, which extend the Pelgrom model for a transistor mismatch. While independently conceived and pursued, similar and complementary conclusions have been reported by these groups, refining the understanding of a transistor mismatch to encompass halo-dominated transistor designs. [ABSTRACT FROM AUTHOR]

Vertically stacked junctionless accumulation mode (JLAM) nanowire field effect transistors (NWFETs) outperform inversion-mode (IM) NWFETs below 10-nm technology nodes, but the vertical stacking of nanowires (NWs) has a constraint of position dependent drain current. This paper encompasses: 1) extensive investigation of the impact of series resistance on IM, JL mode, and JLAM NWFET architectures; 2) a proposed approach to mitigate the series resistance; and 3) linearity assessment of stacked JLAM-NWFET for radio frequency (RF) applications. We have suggested that by decreasing the channel doping in the bottom NW with respect to the top NW in a stack, the current can be significantly improved along with the reduction in series resistance. This improves the overall uniformity of drain current in each NW for stacked JLAM-NWFET. The linearity performance of the device is assessed in terms of following figure of merits (FOMs): IIP3, 1-dB compression point, and higher order derivative of transconductance ${g}_{m\textsf {2}}$ and ${g}_{m\textsf {3}}$. These FOMs are evaluated through numerical simulations using Sentaurus Technology Computer-Aided Design to confirm the robustness of the device against intermodulation distortion making it suitable for low power radio frequency integrated circuit design applications. The proposed solution allows higher drive current, improved linearity, and thus lower distortion in stacked JLAM-NWFET. [ABSTRACT FROM AUTHOR]