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A split dc-link dual-active-bridge (SDLDAB)-based multiport converter (MPC) is proposed in this article. The intended application of the SDLDAB converter is to interface two solar photovoltaic (PV) modules and a battery bank with a dc microgrid. Depending upon the prevailing atmospheric condition, these two solar PV modules can be operated at their maximum power points. This is achieved by maintaining appropriate voltages at the input terminals of the two PV modules. A high-frequency transformer is employed to provide high voltage gain between the dc microgrid and PV as well as battery ports. A direct power flow path is established between the solar PV modules and the battery without involving the transformer. The transformer current is minimized by appropriately modulating the switching sequence of the SDLDAB. Detailed simulation studies are carried out to predict the performance of the system. A laboratory prototype of the SDLDAB having 1-kW power rating is fabricated. The performance of the MPC is validated by carrying out detailed experimental studies on the developed prototype. [ABSTRACT FROM AUTHOR]

In recent years, modular multilevel converter (MMC) is considered for medium-voltage variable speed drives (VSD) due to its modularity and higher reliability. However, the major drawback of the MMC-based VSD is the higher capacitor ripple voltage at lower operating speeds. In literature, this ripple voltage is reduced by injecting a high-frequency circulating current into each arm. This additional circulating current increases the overall current rating of the devices, inductors, and capacitors. Alternatively, the capacitor ripple voltage can be reduced at the lower output frequency by reducing the dc-bus voltage. This paper proposes a new configuration using a multipulse diode-bridge rectifier to reduce the dc-bus voltage when the drive is operated at lower speeds. Therefore, the capacitor ripple voltage decreases without injecting any circulating current. In addition, a new technique is proposed to maintain the peak-to-peak value of the submodule capacitor ripple voltage constant at near-zero speed. The proposed converter with 24-pulse rectifier configuration is simulated in MATLAB/Simulink, and the experimental validation is carried out on a prototype with 12-pulse rectifier. [ABSTRACT FROM AUTHOR]

A single-stage, bidirectional, current-source converter (CSC) topology to interface a dc microgrid with an ac grid is reported in the literature. In this topology, under a balanced grid voltage condition, the dc-link inductor current can be regulated over a wide range—from zero to rated value—while the ac-side current has low harmonic distortion. However, unbalanced grid voltages result in second-harmonic pulsation in the current and power on the dc side of the converter. In addition, the ac-side currents will be unbalanced due to the presence of a negative-sequence component. This would result in undesired tripping of the converter if one of the phase currents exceeded its rated value. Various control loop structures for the operation of voltage-source converter under unbalanced grid voltage conditions are reported in the literature. However, use of similar control loop structures for CSC may lead to unstable operation. Therefore, a control scheme to inject balanced three-phase currents into the ac grid under an unbalanced grid voltage condition is proposed in this paper. The stability of the proposed control scheme is studied using a small-signal model of the converter. Performance of the proposed control scheme is studied using MATLAB/Simulink and is experimentally validated. [ABSTRACT FROM AUTHOR]

A paralleled multilevel inverter topology consists of n three-phase three-level current-fed inverters (CFIs) connected in parallel on ac side. AC currents with (2n+1) levels can be generated utilizing redundant switching states when all three-level inverters have equal dc-link currents. However, the multilevel space vector diagram gets modified, redundancy in the switching states is lost and the multilevel current pattern changes when the dc-link current of all inverters is not the same. This introduces low-frequency harmonics in output current, thereby deteriorating total harmonic distortion (THD). The presence of low-frequency components in the output current could be avoided by selecting suitable switching state vectors and ensuring proper time sharing among these vectors. Two methods to select such switching state vectors are proposed in this paper. In the first method, a reference current space vector is realized using the nearest switching state vectors. However, this method results in low-frequency pulsation in dc-link voltage of each inverter. In the second method, the switching state vectors are chosen to eliminate this low-frequency pulsation. Effectiveness of these methods is experimentally validated for a five-level CFI. Further, performance of these methods is compared based on efficiency, THD, and dc-link voltage ripple for various inequality ratios in dc-link currents. [ABSTRACT FROM AUTHOR]