Search

In this study, we investigate the effects of intentional crosstalk noise on modern Multi-Processor System-on-Chips (MPSoCs). We demonstrate the potential for an adversary to inject false data into the communication network of the MPSoC, thereby creating intentional crosstalk scenarios that increase the likelihood of bit errors in other users’ data. This is achieved through a pre-attack reconnaissance phase in which the attacker determines the size of the MPSoC’s communication links. Based on this information, the attacker then issues false packets into the MPSoC’s network to intentionally corrupt users’ data. Our evaluations confirm that the attack can have serious consequences, altering the on-chip communication system of MPSoCs. Additionally, we propose a multi-layer defense mechanism that ensures the proper functioning of the MPSoC in the presence of both benign and malicious crosstalk scenarios. Our experimental results confirm the effectiveness of our proposed method in addressing at least 88% of the crosstalk situations with minimal power and performance overhead compared to alternative solutions.

2D-NoCs have been the mainstream approach used to interconnect multi-core systems. 3D-NoCs have emerged to compensate for deficiencies of 2D-NoCs such as long latency and power overhead. A low-latency routing algorithm for 3D-NoC is designed to accommodate high-speed communication between cores. Both simulation and analytical models are applied to estimate the communication latency of NoCs. Generally, simulations are time-consuming and slow down the design process. Analytical models provide, within a fraction of the time, nearly accurate results which can be used by simulation to fine-tune the design. In this paper, a high performance and adaptive routing algorithm has been proposed for partially connected 3D-NoCs. Latency of the routing algorithm under different traffic patterns, different number of elevators and different elevator assignment mechanisms are reported. An analytical model, tailored to the adaptivity of the algorithm and under low traffic scenarios, has been developed and the results have been verified by simulation. According to the results, simulation and analytical results are consistent within a 10 percent margin. [ABSTRACT FROM AUTHOR]

3D ICs can take advantage of a scalable communication platform, commonly referred to as the Networks-on-Chip (NoC). In the basic form of 3D-NoC, all routers are vertically connected. Partially connected 3D-NoC has emerged because of physical limitations of using vertical links. Routing is of great importance in such partially connected architectures. A high-performance, fault-tolerant and adaptive routing strategy with respect to the communication flow among the cores is crucial while freedom from livelock and deadlock has to be guaranteed. In this paper we introduce a new routing algorithm for partially connected 3D-NoCs. The routing algorithm is adaptive and tolerates the faults on vertical links as compared to the predesigned routing algorithms. Our results show a $40-50\%$ improvement in the fraction of intact inter-level communications when the fault tolerant algorithm is used. This routing algorithm is light-weight and has only one virtual channel along the $Y$ dimension. [ABSTRACT FROM AUTHOR]