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The BeamCal detector, one of the calorimeters in the forward region of the International Linear Collider detector, will serve three purposes: ensure hermeticity of the detector for small polar angles, reduce the backscattering from beamstrahlung electron-positron pairs into the detector center, and provide a low-latency signal for beam diagnostics. The BeamCal specifications in terms of noise suppression, signal charge, pulse rate, and occupancy pose unique challenges in the front end and readout electronics design. The Bean–BeamCal instrumentation IC is the integrated circuit under study to fulfill these requirements. To process the signal charge at the International Collider pulse rate, the Bean uses switched-capacitor filters and a slow reset-release technique. Each channel has a 10-bit successive approximation analog-to-digital converter. The Bean also features a fast feedback adder capable of providing a low latency output for beam diagnostic purposes. This work presents the design and characterization of a 3-channel prototype of the Bean built to validate concepts while the final device will comprise 32 channels. [ABSTRACT FROM PUBLISHER]

Addresses the system analysis and description, controller design and real demonstrations of a low-cost altitude control system for the Kadet Senior radio-controlled airplane. Relationship between altitude and output voltage for the altitude sensor; Application in an automatic control course.

Ferroelectric (FE) materials are being studied for a variety of applications in memory, logic, and neuromorphic computing, for which predictive models of FE polarization are essential. In this paper, we present a Monte Carlo simulation framework capable of predicting the dynamic, history-dependent response of an FE under arbitrary input waveforms. The simulation is developed by generalizing the physics-based nucleation-limited switching model for polarization reversal in a polycrystalline FE. Measured polarization reversal data from fabricated FE Hf0.5Zr0.5O2 capacitors are used to extract the statistical distribution of FE grains. After parameter extraction, the model is able to predict the dynamics of the FE capacitor without further calibration. Finally, the model is applied to characterize the dynamic response of FE–dielectric bilayer structures and quantify the reduction in memory window due to device variability. [ABSTRACT FROM AUTHOR]

Discrete-time filters represent a promising solution for pulse-processing in high-energy physics experiments due to their flexibility, reliability, and their capability to synthesize weighting functions with virtually any shape. One of the major concerns when designing one of these filters is to calculate the filter parameters that maximize the signal-to-noise ratio. The classic way to address this problem is to perform the noise analysis using a continuous-time domain approach based on the weighting function concept. However, when addressing the problem from an inadequate time domain, the analysis is not insightful and the resulting expressions are complex and difficult to use for design purposes. In this work, a mathematical framework for a design-oriented analysis of discrete-time filters in the discrete-time domain is presented. This analysis is based on treating the sampled noise as a discrete-time signal, which can be manipulated to obtain a closed-form expression for the front-end noise, suitable for computer automatic evaluation and filter optimization procedures. An example of the optimum filter formulation and computation is presented, in addition to several conclusions about optimum digital filtering. [ABSTRACT FROM PUBLISHER]

Charge amplifiers represent the standard solution to amplify signals from capacitive detectors in high energy physics experiments. In a typical front-end, the noise due to the charge amplifier, and particularly from its input transistor, limits the achievable resolution. The classic approach to attenuate noise effects in MOSFET charge amplifiers is to use the maximum power available, to use a minimum-length input device, and to establish the input transistor width in order to achieve the optimal capacitive matching at the input node. These conclusions, reached by analysis based on simple noise models, lead to sub-optimal results. In this work, a new approach on noise analysis for charge amplifiers based on an extension of the gm/ID methodology is presented. This method combines circuit equations and results from SPICE simulations, both valid for all operation regions and including all noise sources. The method, which allows to find the optimal operation point of the charge amplifier input device for maximum resolution, shows that the minimum device length is not necessarily the optimal, that flicker noise is responsible for the non-monotonic noise versus current function, and provides a deeper insight on the noise limits mechanism from an alternative and more design-oriented point of view. [ABSTRACT FROM PUBLISHER]