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Outsourcing of the design and IC fabrication to the untrusted entities increases the risk of hardware Trojan insertion in different stages of IC’s life cycle. In this brief, we propose a pre-silicon modification scheme, aiming at detecting and compensating the adverse effect of timing hardware Trojans (THT) using a time borrowing approach. The key idea is that a circuit path under tamper in which the setup time is violated can borrow some time from the following stage if it has enough positive timing slack to donate. Accordingly, we modify the original circuit by employing the Dynamic flip-flop Conversion (DFFC) structures to convert the suspected flip-flops into a single transparent latch. A new timing vulnerability analysis including the path-delay and structural analysis along with the proposed test pattern generation scheme is also developed to exploit the vulnerable paths suitable for DFFC insertion. The experimental results show that the insertion of DFFC structures can effectively predict timing errors higher than 1.4% of the critical path-delay while it can fully restore the Trojan-infected paths back to its normal state by compensating 100% of the injected delays ranging from 39% to 81% of the critical path. [ABSTRACT FROM AUTHOR]

With the rapid growth in IC outsourcing in the semiconductors industry, concerns have increased about the weakening ICs security against hardware Trojan attacks. In this brief, an integrated hardware Trojan detection and localization methodology is presented by employing the proposed SAT-based test pattern generation scheme and the MUX-based debugging technique. The experimental results show that our methodology can effectively detect timing anomalies in the path-delays caused by hardware Trojans with node coverage around 97% as well as localizing all Trojan’s gates with a localization resolution around 99.6%. Moreover, all timing error sites are successfully identified with zero False Negative and 0.56% False Positive rates. [ABSTRACT FROM AUTHOR]

The continuously growing complexity of digital circuits and shortening time-to-market has put pressure on the verification methodology. To reach this goal, automatic correction of design bugs has become necessary. Existing methods for automatic correction, suffer from consuming so much time and memory usage which makes them mostly inapplicable for large circuits. Our main idea to come up with a solution is reusing partially corrected circuits in the process of finding the final solution. Experimental results show that, in comparison with existing methods, our method can accurately detect bugs and correct them up to $2.3\times $ faster with less than half of memory usage in comparison with existing methods due to decreasing the number of generated solutions by $2.1\times $ and reducing the size of the SAT problem by $3\times $. [ABSTRACT FROM AUTHOR]

High computational complexity and power consumption makes convolutional neural networks (CNNs) ineligible for real-time embedded applications. In this brief, we introduce a low power and flexible platform as a hardware accelerator for CNNs. The proposed architecture is fully configurable by a software library so that it can perform different CNN models with a reconfigurable hardware. The hardware accelerator is evaluated on a ZC706 evaluation board. We make use of the AlexNet architecture in a real-time object recognition application to demonstrate the effectiveness of the proposed CNN accelerator. The results show that the performance rates of 198.1 GOP/s using 512 DSP blocks and 23.14 GOP/s using 64 DSP blocks are achievable for the convolution and fully connected layers, respectively. Moreover, images are processed at 82 frames/s, which is significantly higher than existing implementations. [ABSTRACT FROM AUTHOR]

Hardware Trojan attacks have emerged as a major security issue for hardware at different level of abstractions, which relate to malicious tampering of a hardware during design or fabrication process. In this paper, a new low overhead and high speed design for trust methodology for increasing both full activation and side channel sensitivity of Trojan is proposed. The main idea is that the increase in transition probability of individual nets does not necessarily increase the transition probability of the succeeding nets of the circuit. Accordingly, the rules and conflicts of the propagation of maximum transition probability for individual gates have been presented to ensure that a full transition path is constructed between each low transition probability net and primary inputs of the circuit. The results show that the proposed methodology achieves superior efficiency in Trojan full activation by more than $4 \times $ through logic testing approach besides higher sensitivity averagely around $20 {\times }$ for power-based side channel analysis compared to existing methods. [ABSTRACT FROM AUTHOR]

Good knowledge of internal circuit states are crucial for efficient post-silicon debug. Due to the area, power, routing, and bandwidth limitations trace buffer-based design for debug hardware provides execution traces of a limited number of state elements which are then usually expanded through signal restoration. In this paper, we propose to record combinational execution traces and show that combined with signal restoration better knowledge of internal circuit states are obtained. Our experiment with benchmark circuits show that restoration quality in terms of state restoration ratio is improved up to 48% on average. Extending the solution space by, including combinational gates drastically increases signal selection runtime. Using hybrid signal selection methods, we also provide good tradeoff between restoration quality and runtime. By dynamically updating some metrics in state-of-the-art hybrid selection method, we achieve 65% reduction in runtime with only 2% penalty in solution quality. Using the proposed signal selection algorithms, designers can better explore the circuit states and achieve more efficient post-silicon debug. [ABSTRACT FROM AUTHOR]

In recent years, using distributed fiber-optic sensors based on Brillouin scattering, for monitoring pipelines, tunnels, and other constructional structures have gained huge popularity. However, these sensors have a low signal-to-noise ratio (SNR), which usually increases their measurement error. To alleviate this issue, ensemble averaging is used which improves the SNR but in return increases the measurement time. Reducing the noise by averaging requires hundreds or thousands of scans of the optical fiber; hence averaging is usually responsible for a large percent of the entire system latency. In this paper, we propose a novel method based on artificial neural network for SNR enhancement and measurement acceleration in distributed fiber-optic sensors based on the Brillouin scattering. Our method takes the noisy Brillouin spectrums and improves their SNR by 20 dB, which reduces the measurement time significantly. It also improves the accuracy of the Brillouin frequency shift estimation process and its latency by more than 50% in comparison with the state-of-the-art software and hardware solutions. [ABSTRACT FROM AUTHOR]

Time borrowing techniques have been widely used to mitigate the timing errors in high-performance designs. A new dynamic flip-flop conversion technique is introduced by Ahmadi et al. (2015) which dynamically converts flip-flops into transparent latches to grant the time borrowing from the next stage and prevent setup time violation. However, it is not able to prevent the timing violation in the successive critical path (SCP) and critical feedback path (CFP) structures. In this brief, we introduce a novel idea of using the output of fast prediction logic of the critical path along with dynamic clock stretching in SCP and CFP structures. The results show that our technique, on average, is able to improve the performance by 20.2% and 14.8% during the prelayout and postlayout simulations, respectively. Furthermore, the proposed technique is almost 7.7% more effective in terms of the performance improvement with only 0.1% area overhead in comparison with the best existing technique. [ABSTRACT FROM AUTHOR]

As the complexity of digital designs continuously increases, existing methods to ensure their correctness are facing more serious challenges. Although many studies have been provided to enhance the efficiency of debugging methods, they are still suffering from the lack of scalable automatic correction mechanisms. In this paper, we propose a method for correcting multiple design bugs in gate level circuits. To reduce the correction time, an incremental satisfiability-based mechanism is proposed which not only does not require a complete set of test patterns to produce a gate level implementation which does not exhibit erroneous behavior, but also will not reintroduce old bugs after fixing new bugs. The results show that our method can quickly and accurately suggest corrected gates even for large industrial circuits with many bugs. Average improvements in terms of the runtime and memory usage in comparison with existing methods are ${2.8 \times }$ and ${{6.5 \times }}$ , respectively. Also, the results show that our method compared to the state-of-the-art methods needs ${{2.6 \times }}$ less test patterns. [ABSTRACT FROM AUTHOR]

Having an automatic tool capable of completing all steps of debugging including correction specially for complex designs such as modern processors is ideal for every debugging engineer. Although in theory, quantified Boolean formulas (QBFs) can be used to formulate this class of problems effectively, current solvers are still too immature for accomplishing this goal. In this paper, we propose a scalable symbolic simulation-based method utilizing QBF to correct the candidate bug locations in abstract formal models. We assume that candidate bug locations are determined already, the bug is located in bit-level logic, and the input arguments are known. We define correcting functions and adjust their parameters by formulating the problem as QBF and solving it using symbolic simulation-based method. To further improve scalability, we propose dynamic pruning which breaks the main problem into several smaller subproblems. The efficiency of the proposed method is proved by solving problems for which existing methods are not capable of providing results. [ABSTRACT FROM AUTHOR]

In recent years, due to the rapid developments of the technology, distributed optical fiber sensors based on Brillouin scattering have become widely popular. Despite their major role in modern monitoring systems, there have been a few works about the challenges of data acquisition and data analysis in such systems. These sensors have a sensing distance of tens of kilometers, which result in a massive amount of raw data. To process this amount of data, millions of operations are needed, which can be quite challenging in an online monitoring system. In this paper, we propose a hardware architecture for analysis of acquired data from the optical part of these sensors. Our main focus is on the performance and utilization of field programmable gate array resources. We also propose a novel estimator based on moving average and cross correlation, which improves the performance of the estimation process more than 95% in comparison with the state-of-the-art software and hardware solutions. [ABSTRACT FROM PUBLISHER]

The increasing demand for lower power forces designers to use sophisticated power management strategies such as multivoltage and power gating which are often accompanied with many design bugs. Correcting such bugs can be a timeconsuming process that requires considerable manual efforts. In this paper, we propose a scalable automated method for correcting dynamic power management architectures by an incremental SAT-based mechanism. First, an initial counterexample (CEX) is generated by checking the equivalency between the specification model of the processor and its buggy implementation model. Then, we find two candidate solutions instead of one to satisfy this CEX. If two solutions are not equivalent, we generate new CEX in an iterative process which effectively converges into the final solution. The proposed method enables designers to correct multiple bugs such as missing isolation cells between two power domains, disordering in the sequence of control signals, error in the data restoring or saving, and powering off in always-on domains which are not addressed by existing methods. We have shown the effectiveness of our method on modern processors supporting complex power management mechanisms. The results confirm that our proposed method, respectively, reduces symbolic simulation steps and runtime by 2.33× and 47.93× compared to the state-of-the-art methods. [ABSTRACT FROM AUTHOR]

In range analysis (RA), suitable integer bit-widths are assigned to the variables so that no overflow occurs. Although the accuracy in RA rather than error analysis has more impact on hardware cost and efficiency, there are few works that offer new approaches to improve RA. Arithmetic functions, mostly represented by polynomials, are normally suitable for both optimization and verification purposes. In this paper, a safe and more accurate RA of feed-forward fixed-point polynomial data-flow graphs is proposed. The method employs particular features of RA and maps it to a specific class of polynomial optimization problems. The proposed method provides tighter ranges while taking less runtime in comparison with satisfiability-modulo theory-based method. Furthermore, the improved ranges lead to enhance the area and delay efficiency more than 50% and 24%, respectively, when the circuits are implementing the functions in comparison with the state-of-the-art techniques. [ABSTRACT FROM PUBLISHER]

In this brief, we introduce an architecture for accelerating convolution stages in convolutional neural networks (CNNs) implemented in embedded vision systems. The purpose of the architecture is to exploit the inherent parallelism in CNNs to reduce the required bandwidth, resource usage, and power consumption of highly computationally complex convolution operations as required by real-time embedded applications. We also implement the proposed architecture using fixed-point arithmetic on a ZC706 evaluation board that features a Xilinx Zynq-7000 system on-chip, where the embedded ARM processor with high clocking speed is used as the main controller to increase the flexibility and speed. The proposed architecture runs under a frequency of 150 MHz, which leads to 19.2 Giga multiply accumulation operations per second while consuming less than 10 W in power. This is done using only 391 DSP48 modules, which shows significant utilization improvement compared to the state-of-the-art architectures. [ABSTRACT FROM AUTHOR]

Although using presilicon information in postsilicon debugging phase seems interesting, space and time limitations of existing formal verification tools restrict the possibility of this idea. In this paper, the effective usage of presilicon information to enhance postsilicon trace signal selection in modern processors is discussed. Furthermore, a novel architecture for dynamic per-cycle selection of signals based on the present instruction is implemented and synthesized. In presilicon phase, first, a set of controlling signals and their corresponding rules are extracted manually. Based on these rules, a set of data from model is extracted using an automatic formal method, which determines which signals should be traced at postsilicon according to the values of controlling signals. This mechanism alone results in an average of 79% and 54% bits to be pruned from the traceable signals for Leon3 and multithreaded DLX processors and 86% and 75% improvement when used in conjunction with traditional methods, respectively. [ABSTRACT FROM AUTHOR]

In this brief, we propose novel methods to systematically explore the design space of floating-point expressions on a field-programmable gate array in order to extract a nondominated set that covers the whole design space in terms of the accuracy, area, and run-time numbers. We first introduce a regular selection method that consists of two main phases: 1) generating equivalent expressions and 2) using a Pareto algorithm to extract a nondominated set. Then, we introduce a fast selection method in which two phases are composed in order to speed up the optimization process, while the quality of the final results does not change significantly. The results show that regular selection enjoys up to a 35.3% run-time improvement in comparison with the state-of-the-art techniques. Furthermore, the fast selection method is approximately 45× faster than the regular selection. [ABSTRACT FROM PUBLISHER]

Field-programmable gate arrays (FPGAs) could outperform microprocessors on floating point computations due to massive parallelism, freedom on the selection of exponent/mantissa width, and utilization of simplified adders and multipliers. However, optimized use of resources and accuracy of the final implemented expression are two important issues in the implementation of floating point arithmetic expressions on FPGAs. High-level optimizations such as changing the form of floating point initial expression by arithmetic rules or deciding on the exponent and mantissa widths have significant effects on the resource usage, accuracy, and efficiency of the final implementation. In this paper, we introduce an optimization framework called OptiFEX, which enables designers to optimize an initial floating point expression in terms of the resource usage and the exponent and mantissa widths based on: 1) input intervals; 2) the smallest presentable number in the implementation; and 3) the maximum permitted error interval provided by the designer. First, we come up with some techniques to generate equivalent expressions for the initial expression, and we make use of some heuristics to speed up the process of equivalent expressions’ generation. We also propose a method to estimate the mantissa width. Finally, we introduce an algorithm to choose the best expressions in terms of the resource usage based on the estimated mantissa and exponent widths. [ABSTRACT FROM AUTHOR]

A challenging verification and optimization problem in computer arithmetic and embedded systems is error analysis (EA) of fixed-point polynomial data-flow graphs (DFGs). This brief presents an EA framework to compute the error measure maximum mismatch of feedforward fixed-point polynomial DFGs. Our idea to reduce the overestimation keeping efficiency is introducing a unified analytical framework for the two most popular self-validated numerical methods, i.e., interval arithmetic (IA) and affine-arithmetic (AA), so that correlated arguments appear in suitable positions in the DFG. The results show that our methods can enhance error accuracy, in average, more than 24% in comparison with the state-of-the-art techniques while keeping the efficiency of IA and AA. [ABSTRACT FROM PUBLISHER]

Dynamic flip-flop (FF) conversion is a method of time borrowing (TB) for improving the performance of digital systems prone to variations. The first type of this method (Type A), which was previously presented, suffers from a large inefficient transparency window. In this brief, we present an improved structure for this method (Type B) that mitigates this problem by automatically closing the window after the arrival of late data at timing critical FFs. This method was compared with soft edge FF and dynamic clock stretching through simulations on different ITC’99 benchmarks. We defined a parameter called improvement efficiency, which is the ratio of the timing yield improvement to the power overhead of TB. According to the simulation results, the efficiency of Type A is on average 269% more than the best results of other methods when considering only the setup time violations. But, when taking both the setup time and the hold time violations into account, Type B is on average 46% more efficient than the best results of other methods. The simulations also show that the yield improvement of this method increases in higher clock frequencies and it remains the most efficient method when reducing the voltage down to near-threshold region. [ABSTRACT FROM PUBLISHER]