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This brief discusses the limitation of previously published statistical decision feedback equalizer (DFE) models when residual inter-symbol interference (ISI) is present and proposes a method that overcomes this limitation. The paper presents an accurate closed-form expression for the DFE with residual ISI and additive white Gaussian noise (AWGN). The analysis is extended to 4-level pulse amplitude modulation (PAM-4) to cover serial links of current interest. The results verify that the proposed model estimates an accurate bit error rate (BER). [ABSTRACT FROM AUTHOR]

This work presents a RISC-V system-on-chip (SoC) with eight application cores containing programmable-precision vector accelerators. The SoC is built by using a generator-based design methodology, which enables the integration of open-source and project-specific building blocks to develop differentiated functionality. The digital component generators use Chisel, the analog component generators use the Berkeley Analog Generator (BAG), and the physical design flow is implemented with Hammer. The chip totals 125 M gates and is implemented in a 16-nm finFET process. The vector accelerator achieves peak energy efficiency per task of 209 half-precision, 92 single-precision, and 56 double-precision GFLOPs/W for a matrix multiplication kernel at 0.55 V and 339 MHz. [ABSTRACT FROM AUTHOR]

This article presents a 200-Gb/s pulse amplitude-modulation four-level (PAM-4) and 100-Gb/s non-return-to-zero (NRZ) transmitter (TX) in 28-nm CMOS technology. To achieve the target data rate, the output bandwidth and swing of the proposed TX are optimized by minimizing the output capacitance of the 4:1 multiplexer (MUX) and driver stage with pull-up current sources and adopting a fully reconfigurable 5-tap feed-forward equalizer (FFE). The key circuit includes a segmented 8:4 MUX and 4:1 MUX/driver, a thermal encoder and retimer, and a flexible clock distribution network. Using the layout generated with Berkeley Analog Generator (BAG), the proposed TX achieves an eye opening with >52.9-mV eye height, 0.36 UI eye width, >98% RLM, and 4.63 pJ/b at 200-Gb/s PAM-4 signaling under >6-dB channel loss at 50 GHz, demonstrating the highest data rate achieved using a planar process. [ABSTRACT FROM AUTHOR]

This article presents a 71–86 GHz 16-element array receiver application-specified integrated circuit (ASIC) for Massive multiple-input–multiple-output (MIMO) wireless uplink, featuring a multiple-output analog beamformer (BF) supporting up to 16 spatially multiplexed users at the same time. The ASIC includes 16 direct-conversion mixer-first RX front-ends, local oscillator (LO) generation and distribution, and a $16\times 16$ fully connected baseband analog beamformer, which derives each user stream as a linear combination of all the 16 antennas. The 16 mm2 28 nm CMOS ASIC is packaged on an organic interposer including a linear patch antenna array. Over-the-air measurements demonstrate up to 2 Gb/s single-user data-rate, and four simultaneous links at 500 Mb/s each, with number of users and data rate only limited by setup constraints. Circuits are optimized for low power consumption in order to enable scaling to massive arrays, and consumes 1.7 W total power, for a power figure of 7 mW/antenna/user. [ABSTRACT FROM AUTHOR]

A 61-MHz Pierce oscillator constructed in 0.35- $\mu \text{m}$ CMOS technology and referenced to a polysilicon surface-micromachined capacitive-gap-transduced wine-glass disk resonator has achieved phase noise marks of −119 dBc/Hz at 1-kHz offset and −139 dBc/Hz at far-from-carrier offsets. When divided down to 13 MHz, this corresponds to −132 dBc/Hz at 1-kHz offset from the carrier and −152 dBc/Hz far-from-carrier, sufficient for mobile phone reference oscillator applications, using a single MEMS resonator, i.e., without the need to array multiple resonators. Key to achieving these marks is a Pierce-based circuit design that harnesses a MEMS-enabled input-to-output shunt capacitance more than $100\times $ smaller than exhibited by macroscopic quartz crystals to enable enough negative resistance to instigate and sustain oscillation while consuming only $78~\mu \text{W}$ of power—a reduction of $\sim 4.5\times $ over previous work. Increasing the bias voltage of the resonator by 1.25 V further reduces power consumption to $43~\mu \text{W}$ at the cost of only a few decibels in far-from-carrier phase noise. This oscillator achieves a 1-kHz-offset figure of merit (FOM) of −231 dB, which is now the best among published chip-scale oscillators to date. A complete linear circuit analysis quantifies the influence of resonator input-to-output shunt capacitance on power consumption and predicts further reductions in power consumption via reduction of electrode-to-resonator transducer gaps and bond pad sizes. The demonstrated phase noise and power consumption posted by this tiny MEMS-based oscillator are attractive as potential enablers for low-power “set-and-forget” autonomous sensor networks and embedded radios. [ABSTRACT FROM AUTHOR]

A 1.89-GHz bandwidth, 175-kHz resolution spectral analysis system-on-chip (SoC), integrating a subsampling analog-to-digital converter (ADC) frontend with a digital reconstruction backend and implementing a 21 600-point sparse Fourier transform based on the fast Fourier aliasing-based sparse transform (FFAST) algorithm has been co-designed by using the Constructing Hardware in a Scala Embedded Language (Chisel) and Berkeley Analog Generator (BAG) circuit generator frameworks in 16-nm CMOS. Three sets of $25\times $ , $27\times $ , and $32\times $ subsampling successive approximation register (SAR) ADCs acquire signal with ~5.4–6.3 effective number of bits (ENOB)/slice. The digital backend consists of mixed-radix 864-, 800-, and 675-point fast Fourier transforms (FFTs), a signal location estimator, and a peeling decoder that recovers aliased signals from a sparsely populated spectrum. A single-issue, in-order, fifth-generation reduced instruction set (RISC-V) Rocket processor interacts with the spectrum analyzer for post-processing and calibration. The ADC consumes 49.8 mW with a 3.78-GHz reference clock. At 400 MHz and 0.7-V digital supply voltage (VDD), the Rocket core and the FFAST digital signal processing (DSP) together consume 133.5 mW. [ABSTRACT FROM AUTHOR]

A single-output, band selecting interposer is designed to combine three identical all-digital CMOS transmitter (Tx) chips. The open-drain CMOS Txs are flip-chip connected to the primary windings of three frequency selecting transformers realized on a single PCB interposer. The secondary windings of the three transformers are connected in series and they share a single output. Across 0.4 to 4 GHz, a peak power higher than 22.9 dBm is achieved collectively by the three sub-Txs with a drain efficiency (DE) better than 25%. The peak powers/DE of the three sub-Txs are 28.6 dBm/50%, 27.4 dBm/49%, and 24.7 dBm/34%, at 0.85, 2.1, and 3 GHz, respectively. This paper further demonstrates that the band selection can be achieved via reconfiguring the CMOS inverse Class-D switching power amplifiers. As demonstrated via continuous wave and 64-quadratic-amplitude modulation, WLAN, and LTE modulation tests, the reconfigurable Tx package exhibits high power and efficiency across all supported bands. [ABSTRACT FROM AUTHOR]

A 700-MHz to 1.6-GHz RF power digital-to-analog converter with programmable integrated harmonic cancellation and mixed-signal filtering is presented. Harmonic cancellation is implemented by splitting the power amplifier (PA) into segments, driving different segments of the PA with phase-shifted versions of the local oscillator (LO) signals, and summing at the output. Mixed-signal filtering is realized in a similar fashion but with segments driven with delayed versions of the input data. The phase shift and data delays are reconfigurable and implemented to operate across a wide frequency range. To boost efficiency, 25% duty cycle LO signals are used. A technique to correct for IQ constellation distortion induced by these 25% duty cycle LO signals is introduced and verified in measurements. The transmitter (TX) operates at a maximum sample rate of 500 MSa/s and achieves an output power of 25.6 dBm for an output load of 100 $\Omega $ when harmonic cancellation is enabled. The TX demonstrates 24–42 dB of 3rd harmonic cancellation for continuous wave signals across a 700-MHz to 2-GHz frequency range, achieving an HD3 as low as −57 dB. The TX achieves an HD3 reduction of 33 dB and an 18-dB notch at 40-MHz offset with 20-MHz long-term evolution data. [ABSTRACT FROM AUTHOR]

Design techniques for a complete 60-Gb/s non-return-to-zero transceiver with adaptive equalization as well as baud-rate clock and data recovery (CDR) are demonstrated. A complete equalization front end with per-path adaptation and per-sampler offset calibration enables 60-Gb/s operation over realistic channels. Current integration in the front end for energy-efficient equalization is combined with integration phase dithering to realize a robust baud-rate CDR. Correlation of the adaptive error sampler output with the phase dithering sequence indicates the direction of phase offset, and the resulting baud-rate CDR saves power and complexity compared to an oversampling CDR by not requiring additional clock phases/deserializers. The proposed 65-nm CMOS transceiver operates at 60 Gb/s with an eye opening of 30% UI and consumes 288 mW while equalizing 21 dB of loss at 30 GHz over a 0.7-m Twinax cable. [ABSTRACT FROM AUTHOR]

This paper demonstrates a wideband CMOS all-digital polar transmitter with flip-chip connection to three high-density-interconnection PCB interposers. The interposers are designed to extract power from a CMOS open-drain inverse Class-D power amplifier core. For a wide frequency range from 0.7 to 3.5 GHz, continuous-wave output power higher than 25.5 dBm and drain efficiency (DE) above 40% are demonstrated. The low-band package achieves a peak power of 29.2 dBm at 1.1 GHz with DE of 60%, the mid-band package outputs 28.8 dBm at 1.5 GHz with DE of 56%, and the high-band package generates 26 dBm at 3 GHz with DE of 49%. The amplitude modulation (AM) is achieved by digitally modulating the switch conductance of the inverse Class-D core, and the on-chip phase modulation is achieved by digitally weighing the in-phase and quadrature bias currents in the IQ mixer. Detailed modulation tests, involving 64 quadrature amplitude modulation (QAM) and 20-MHz WLAN and LTE signals, exhibit excellent power and efficiency at 0.6, 1.2, 1.8, 2.4, 3, and 3.6 GHz. The associated specifications on spectral masks and error vector magnitudes are satisfied. [ABSTRACT FROM AUTHOR]

This paper demonstrates a wideband CMOS all-digital polar transmitter with flip-chip connection to three high-density-interconnection PCB interposers. The interposers are designed to extract power from a CMOS open-drain inverse Class-D power amplifier core. For a wide frequency range from 0.7 to 3.5 GHz, continuous-wave output power higher than 25.5 dBm and drain efficiency (DE) above 40% are demonstrated. The low-band package achieves a peak power of 29.2 dBm at 1.1 GHz with DE of 60%, the mid-band package outputs 28.8 dBm at 1.5 GHz with DE of 56%, and the high-band package generates 26 dBm at 3 GHz with DE of 49%. The amplitude modulation (AM) is achieved by digitally modulating the switch conductance of the inverse Class-D core, and the on-chip phase modulation is achieved by digitally weighing the in-phase and quadrature bias currents in the IQ mixer. Detailed modulation tests, involving 64 quadrature amplitude modulation (QAM) and 20-MHz WLAN and LTE signals, exhibit excellent power and efficiency at 0.6, 1.2, 1.8, 2.4, 3, and 3.6 GHz. The associated specifications on spectral masks and error vector magnitudes are satisfied. [ABSTRACT FROM PUBLISHER]