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Galvanic corrosion generally occurred on Al/Cu bond pads post wafer saw resulted in pitting but no pitting was observed at wafer incoming. There is significant interest in the corrosion behavior of Cu-containing Al alloy, such as PL455, which remain of importance for automotive application due to bondability and reliability safety concern. All of pitting existed Cu precipitation on central of pit holes. A simple experiment simplifies galvanic corrosion condition and reveals its mechanism for definition root cause of pitting. Incoming wafer immerse into di-water in various temperature and air/nitrogen dissolved for 40 and 60 minutes. The experiment results conducted that low temperature and nitrogen dissolved into di-water can suppressed galvanic corrosion however it can't be fully suppressed due to halogen residual on bond pad post CF 4 plasma descum (accelerated corrosion rate) and copper precipitation on Al grain boundary during anneal. Copper precipitated in the Al grain boundary that created Al/Cu galvanic potential and interface, which was galvanic corrosion staring point and then galvanic reaction occurred while Al/Cu couple immersed into electrolyte environment which trigger galvanic corrosion. It interprets galvanic corrosion is observed post wafer saw.

The rapid commercialization of the IEEE 802.11n WLAN standard has increased the demand for higher data-rate and longer-range fully integrated MIMO SoCs that are backward-compatible with legacy IEEE 802.11a/b/g networks. This paper introduces a 3-stream, 3×3 MIMO WLAN SoC that utilizes three antennas to improve throughput, range, and link robustness. This chip integrates three dual-band transceivers, digital physical layer, media access controller, and a PCI express interface in a 65nm CMOS process. Improved EVM is achieved by reducing transmit and receive I/Q mismatch with calibration, and reducing the integrated phase noise with a reference clock doubler.

This paper investigates the time dynamics of online user behavior in a series of overlapping electronic auction mechanisms. An auction is a dynamic game where the valuation and strategic space of bidders determine the final outcomes. When those mechanisms exist concurrently or in a series, multiple sources are visible and accessible, and there is likely to be a form of interdependency. While heterogeneous bidder behavior has been studied in some literature, the focus is mainly on individual auction level and the underlying dynamics regarding the interdependency among the auctions in the market has not been explained. We use two-phased approach. First, we classify user strategy using k-means clustering. Then we characterize the transition pattern of heterogeneous clusters using dynamic systems framework. Long-term behavior of the system is effectively and efficiently predicted using system parameters. Our model can serve as a decision support framework for optimal market design.

This paper introduces a fully integrated 2x2 two-stream MIMO radio SoC that integrates all of the functions of an 802.11n WLAN. The 0.13 mum CMOS radio SoC, which integrates two dual-band (2.4 GHz and 5 GHz) RF transceivers, analog baseband filters, data converters, digital physical layer, media access controller, and a PCI Express interface, provides a low-cost low-power small-form-factor WLAN solution. The MIMO radio comprises two identical dual-band transceivers that share a common frequency synthesizer capable of operating in both integer-N and fractional-N modes. In 2.4 GHz mode, the transceiver uses a direct-conversion architecture with a 3.2 GHz fractional-N frequency synthesizer. Direct conversion is used primarily because of its simplicity and the area reduction it offers by eliminating the need for an IF path. A 3.2 GHz synthesizer frequency is used to avoid VCO pulling. The 3.2 GHz synthesizer output fvco is divided by two and then mixed with the original 3.2 GHz fvco to generate a 4.8 GHz frequency. This 4.8 GHz signal at twice the RF frequency is distributed to both transceivers. Within each transceiver, the 4.8 GHz signal is divided by two to generate the 2.4 GHz in-phase and quadrature LO signals. In the 5 GHz mode, the transceiver uses a sliding-IF dual-conversion architecture, in which the RF and IF LO signals are centered at 2/3 fRF and 1/3 fRF, respectively. The frequency synthesizer, operating in integer-N mode, thus provides a 3.2 GHz RF LO signal that is buffered and distributed to both transceivers. Within each transceiver a resistively loaded divide-by-two circuit is used to generate the quadrature LO signals at 1/3 fRF. The channel center frequencies in the 5 GHz band allow integer-N operation of the synthesizer with a relatively high reference frequency, thus improving the phase noise.