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In this article, a β-Ga2O3 metal-interlayer-semiconductor Schottky barrier diode (MIS-SBD) using Al-reacted aluminum oxide as the interlayer is demonstrated for the first time and compared with conventional metal-semiconductor (MS) Schottky barrier diode (SBD). The aluminum oxide is formed by sputtering a thin Al layer on Ga2O3 substrate and then annealed in O2 at 300 °C. With the insertion of Al-reacted interlayer, the SBD subthreshold swing (SS) is significantly improved to 61 mV/dec with an average current range of > 6 orders. Example of atomic layer deposited (ALD) Al2O3 as the interlayer is also fabricated and characterized. J – V study corrected by Gaussian distribution model shows that all the samples statistically exhibit similar mean barrier heights (BHs). This indicates that the interlayer hardly affects the electrostatic field and band bending as experienced by carrier injections. C – V study provides different BH results in different sample setups. The result proves that Al-reacted interfacial layer helps eliminate interface degradation as compared with ALD Al2O3. Overall, MIS-SBD by Al-reaction method exhibits improved SS, reduced reverse leakage current (I0), low ideality factor, good ON-OFF ratio (> 109), and minimized interface charges as compared with its respective counterparts. The result of this article serves as a promising interface engineering technique for Ga2O3-based SBD designs. [ABSTRACT FROM AUTHOR]

This article presents an analytical method for parameter extraction in oxide semiconductor field-effect transistors (OS FETs), including threshold voltage (VT), effective channel length (Leff), source–drain series resistance (RSD), and intrinsic effective mobility (μint). An analytical expression of effective mobility (μeff) is implemented with the consideration of percolation conduction and RSD effects. This method relies on the concept of Y-function method and the channel length dependent measurement. The extraction results are compared to those from the combination of transfer length method (TLM). It has been shown that a better accuracy of the extracted parameters is achieved with the proposed method. Furthermore, transfer characteristics are resimulated based on the extracted parameters, in which a good match between measurement and simulation is obtained. [ABSTRACT FROM AUTHOR]

The analog resistive switching (RS) characteristics in 2-D polycrystalline (poly-) molybdenum disulfide (MoS2) field-effect transistors (FETs) enable new electronic devices capable of emulating biological synaptic behaviors. In 2-D poly-materials, grain boundary (GB)-induced trap states are of major significance to RS behaviors. However, there is still a lack of appropriate compact models that capture accurate physical mechanisms. Therefore, we developed a surface potential-based compact model, based on the theories of the GB energy barrier and space charge limited current (SCLC). By calibrating to experimental data of MoS2, the physical parameters are extracted, and the model explains the scaling behaviors of channel lengths and grain sizes. Due to the electric-field-induced defect redistribution, the energy barrier modulation at a single-GB (e.g., intersecting GB) quantitatively matches the reported experiments. Moreover, the possible SCLC-based RS behavior is also investigated. Furthermore, we have optimized the set/reset process and simulated the postsynaptic current (PSC) with a tunable potentiation (or depression) process, and then the gate voltage dependence and statistical effects on RS and PSC have been investigated. Thus, this model provides important devices physics insights of 2-D poly-materials and it guides device design, fabrication, and material engineering, to meet the requirements of the future neuromorphic computing application. [ABSTRACT FROM AUTHOR]

Two-dimensional black phosphorus (BP) holds great promise for future nanoscale field-effect transistors owing to its finite bandgap and expected high carrier mobility. Nevertheless, while most studies have reported unipolar p-type or ambipolar BP transistors with a hole conduction dominance, excellent n-type transport in BP has been a critical challenge. Here, we report unipolar n-type BP transistors realized by a MgO capping layer via atomic layer deposition. By coverage with 20-nm-thick MgO, remarkable electron conduction is obtained in transistors fabricated on BP flakes of thicknesses from 2.6 to 7.6 nm, accompanied by fully suppressed hole transport. Furthermore, the unipolar electron transport is found to retain (or even improve) after a period of six months, with the highest extrinsic electron mobility reaching 135.9 cm2/Vs. The effective approach to realizing unipolar n-FETs of BP demonstrated in this letter paves the way to the implementation of BP-based CMOS digital logic circuits. [ABSTRACT FROM AUTHOR]

This paper demonstrates a high-performance black phosphorus nanoribbons field-effect transistor (BPNR-FET) and systematically investigates methods for enhancing its anisotropic carrier transport. The BPNR-FET shows a strong dependence on crystal orientation in which the best mobility performance is achieved in armchair-oriented nanoribbons. A downscaling of nanoribbon width is shown to improve the short-channel effect owing to a better electrostatic gate control. Furthermore, hydrogenation is employed to effectively passivate the dangling bonds and heal the nanoribbon edge defects, leading to nearly hysteresis-free transfer properties. By virtue of bandgap and contact-metal workfunction engineering, n-type BPNR-FET is successfully demonstrated, which enables complementary inverter circuits to be simultaneously realized. This paper unravels the superior performance underscores a conceptually new BPNR-FET, paving the way toward the development of non-planar devices and integrated circuits based on 2-D materials platform. [ABSTRACT FROM AUTHOR]

We report on the improvement of propagation loss in Ge-on-SOI waveguides developed for mid-infrared wavelengths. Strip waveguides of varying widths have been developed in 0.85~\mu \textm thick Ge core and an improvement of up to \sim 3.5 dB/cm has been achieved by annealing the samples at 700 °C for 120 s. The improvement is consistent for both TE and TM polarized light at 3.682~\mu \text{m} . The method is proven feasible for repairing material growth defects and achieving loss performance commensurate with that required for integrated photonics for sensing applications. The minimum propagation loss achieved is \sim 10$ dB/cm after annealing. [ABSTRACT FROM PUBLISHER]

Germanium (Ge) bipolar phototransistors with high-responsivity performance are demonstrated using a low-temperature selective Ge epitaxy process. Large photocurrent and optical response enhancement are achieved over a conventional p-i-n Ge photodetector, which is predominantly attributed to the current gain induced by transistor actions. When illuminated with a photon wavelength of 1.55 μsm, a Ge phototransistor shows a large responsivity of. ∼2.0 A/W for a low operating bias V[subA] of 1.0 V. Optical measurement results further show that good photoresponse could be achieved for a spectral range of 1.31- 1.62 μm, making such a device a very promising option for optical detections in the near-infrared (including L-band) wavelength regime. [ABSTRACT FROM AUTHOR]

The impact of NiPt thickness scaling on total resistance is investigated using short-channel (Lg = \40\ \nm) nm high- k metal-gate complementary SOI MOSFETs with fin widths varying from 500 nm (“planar single-gate thin-body FD SOI FET”) to 25 nm (trigate FET). It is shown that limiting the amount of NiPt available for silicidation becomes increasingly critical as fin width scales due to a reduced silicide-to-silicon interfacial contact area and facilitated silicide encroachment toward the channel. The prevention of Schottky contact by scaling NiPt thickness from 10 to 5 nm on a 20-nm-thick SOI enabled a > \2\times (NFET) and > \6\times (PFET) reduction in total resistance along with swing and DIBL improvements on trigate FETs. [ABSTRACT FROM PUBLISHER]

Double-gate FinFET (\110)\langle \110\rangle and (\100)\langle \100\rangle electron mobility (\mue) and hole mobility (\muh) are experimentally investigated for the following: 1) a wide range of boron and phosphorus fin doping concentrations and 2) a wide variety of gate stacks combining \HfO2, \SiO2, or SiON insulators with TiN or poly-Si electrodes. It is found out that, irrespective of fin doping and gate stack, (\110)\langle\110\rangle\ \mue is competitive with the (\100)\langle\100\rangle\ \mue, while (\110)\langle\110\rangle\ \muh is \geq \2 \times higher than (\100)\langle\100\rangle\ \muh. Inversion \mue and \muh are independent of doping as long as the effective field/doping combination enables the screening of the depletion charge. Mobility degradation with doping is significantly lower in accumulation mode (AM) than in inversion mode (IM) such that, for heavily B-doped fins, AM hole mobility exceeds the IM electron mobility even in (100) FinFETs. In undoped fins, ALD TiN gate stress is observed to improve \mue  for both orientations without degrading \muh. [ABSTRACT FROM AUTHOR]