Search

In this paper, we examine the concept of channel splitting in Gate All Around Tunnel Field Effect Transistor (GAATFET) and its impact on the performance of the device. The TFET device proposed in this work is designed for a channel length of 20nm and the channel region is divided with equal lengths on the same side. The doping concentration has been kept more towards the drain side channel. Numerical simulation using CAD device simulation software has been performed for investigating device performance. Results have been compared with the uniform channel GAATFET. Simulation results show that there is a reduction in off current by 1 decade in the case of split channel GAATFET. Further, a larger difference is found in the electron current density (ECD) of the split channel GAATFET. The subthreshold swing is also found to decrease to a value of 33.14 mV/decade. The threshold voltage was found to be 0.092V.

the reliability and toughness of any SRAM cell is tarnished by miniaturization of device technology because of exponential increase in leakage current components in semiconductor devices. This article presents a novel SRAM cell topology to improve the standby leakage power dissipation, by dynamically varying the Cell Ratio and Pull-up ratio using wordline. The entire SRAM cell evaluation is performed at 45nm CMOS Technology. The standby leakage power dissipation of novel design is reduced to 63% as compared to standard six transistor based SRAM cell (6T). The read mode noise margin of novel design becomes 1.056× times than 6T SRAM cell. Further, the effect of process variation also considered for simulation. It also verifies that the novel design offers 8.30nW average (or mean) standby leakage power dissipation as compared to 13.60nW in 6T.

In this paper, we study the source drain Gaussian doping profile of strained In 0.53 Ga 0.47 AS based high electron mobility FinFET transistor (HEMT). The Gaussian doping profile is created using Pearson distribution model by setting the values of the gamma and beta parameters (the function characterizing the amorphous part of the profile). The ON current increases exponentially and the step doping also reduces the ON resistance, hence mobility increases. The proposed doping profile gives 2000 mA current for 30 nm gate length HFET.

This paper presents a Cylindrical GAA TFET based on germanium source for low power applications. The proposed device used the merits of low band gap material such as germanium, which is used as a material in the source region. Device investigations have been made in terms of DC characteristics like I ON , I OFF , SS, I ON /I OFF . The proposed device increases ON-current as high as 1.9 × 10−5 A/μm, which corresponds to 7 × improvement in I ON /I OFF ratio when compared with the Si-GAA-TFET. Whereas, drain underlap causes increase in series resistance across drain-channel junction, which reduces the electric field by increasing the tunneling barrier width at the drain side, significantly reduced off-state leakage current. This shows the better device performance to address the requirement of ultra-low power applications.

This paper presents a novel subthreshold Darlington pair based negative bias temperature instability (NBTI) monitoring sensor under the stress conditions. The Darlington pair used in the circuit provides the stability of the circuit and the high input impedance of the circuit makes it less affected by the PVT variations. The proposed sensor provides the high degree of linearity and sensitivity under subthreshold conditions. The sensitivity of the proposed sensor is 8.15 μV/nA and also the sensor is less affected by the process variation and has the deviation of 0.0011 mV at standby leakage current of 30 nA.

In this work, systematic investigation of DGTFET have been made by varying different device parameter such as dielectric constant, doping concentration, work function, temperature, and channel length with their variation impact on threshold voltage (Vth). It is also analyzed that while decreasing the value of work function, energy band overlap increases, whichcauses decrease in tunneling width. Hence leads to highsource channel tunneling. DC characteristics of theproposed device like ON current, OFF current and Vth arealso examined with different device parameter engineering. TCAD device simulator was used as a 2D simulator for the optimization result of DG-TFET.

In this paper, we analyze the effects of single-chargetrapinduced random telegraphic noise (RTN) on asymmetricdual high-K spacer based FinFET (ADS-FinFET). The effectsof RTN reduces in proposed device because asymmetric high-K spacer reduces the electric field effect at source and formation of the barrier between source to gate/drain. The spacer width optimization will provide maximum possible performance and tolerant towards RTN at 12 nm high-K spacer width. Reduced equivalent oxide thickness (EOT) also help to reduce RTN effect whereas, RTN impact increases with device scaling.