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Homomorphic encryption becomes one of the key components in many emerging applications, e.g., cloud computing, to achieve privacy-preserving data processing. However, one of the major drawbacks that precludes the widespread adoption of homomorphic encryption is the huge expansion of the ciphertext. This problem becomes even more severe when multimedia data (images/videos) are handled, as these files are essentially of large sizes. This work addresses this challenging issue and proposes a strategy of reducing the ciphertext expansion in image homomorphic encryption. To this end, a randomly selected subset of the pixels are encrypted using homomorphic cryptosystem to form one part of the ciphertext. The remaining pixels are encrypted by relating them with this random subset through a linear interpolation technique. The whole homomorphically encrypted image can be obtained, upon receiving all the ciphertexts, by exploiting the homomorphic property and the linearity. It is demonstrated that the proposed scheme is secure, and is capable of achieving significant reduction of the ciphertext expansion, while perfectly preserving the homomorphic property. © 2015 IEEE.

Homomorphic encryption becomes one of the key components in many emerging applications, e.g., cloud computing, to achieve privacy-preserving data processing. However, one of the major drawbacks that precludes the widespread adoption of homomorphic encryption is the huge expansion of the ciphertext. This problem becomes even more severe when multimedia data (images/videos) are handled, as these files are essentially of large sizes. This work addresses this challenging issue and proposes a strategy of reducing the ciphertext expansion in image homomorphic encryption. To this end, a randomly selected subset of the pixels are encrypted using homomorphic cryptosystem to form one part of the ciphertext. The remaining pixels are encrypted by relating them with this random subset through a linear interpolation technique. The whole homomorphically encrypted image can be obtained, upon receiving all the ciphertexts, by exploiting the homomorphic property and the linearity. It is demonstrated that the proposed scheme is secure, and is capable of achieving significant reduction of the ciphertext expansion, while perfectly preserving the homomorphic property. © 2015 IEEE.

Image demosaicking or color filter array interpolation is a process of interpolating missing color samples to reconstruct a full color image. In general, existing algorithms assume that the high frequency components such as edges, texture etc. of different color channels are similar and thus take an advantage of it to estimate the missing samples. In this pa-per, we efficiently analyze the relationships of intra and inter-color correlation among the channels and observe that such assumption fails in most cases. In view of this observation, we propose a scheme that exploits the correlation between different color channels much effectively than the existing al-gorithms. Experimental results demonstrate that the proposed algorithm outperforms the existing methods both in terms of Peak Signal to Noise Ratio (PSNR) and visual perception. Index Terms— Bayer color filter array, color difference interpolation, high frequency components, demosaicking.

Depth map compression is important for efficient network transmission of 3D visual data in texture-plus-depth format, where the observer can synthesize an image of a freely chosen viewpoint via depth-image-based rendering (DIBR) using received neighboring texture and depth maps as anchors. Unlike texture maps, depth maps exhibit unique characteristics like smooth interior surfaces and sharp edges that can be exploited for coding gain. In this paper, we propose a multi-resolution approach to depth map compression using previously proposed graph-based transform (GBT). The key idea is to treat smooth surfaces and sharp edges of large code blocks separately and encode them in different resolutions: encode edges in original high resolution (HR) to preserve sharpness, and encode smooth surfaces in low-pass-filtered and down-sampled low resolution (LR) to save coding bits. Because GBT does not filter across edges, it produces small or zero high-frequency components when coding smooth-surface depth maps and leads to a compact representation in the transform domain. By encoding down-sampled surface regions in LR GBT, we achieve representation compactness for a large block without the high computation complexity associated with an adaptive large-block GBT. At the decoder, encoded LR surfaces are up-sampled and interpolated while preserving encoded HR edges. Experimental results show that our proposed multi-resolution approach using GBT reduced bitrate by 68% compared to native H.264 intra with DCT encoding original HR depth maps, and by 55% compared to single-resolution GBT encoding small blocks. © 2012 IEEE.

Subpixel-based down-sampling is a method that can potentially improve the apparent resolution of a down-scaled image by controlling individual subpixels rather than pixels. However, the increased luminance resolution often comes at the price of chrominance distortion. A major challenge is to suppress color fringing artifacts while maintaining sharpness. In [1], we proposed a novel human visual quality based (HVS) subpixel downsampling method. In this paper, we propose a hardware-friendly subpixel based downsampling scheme based on our previous work which can achieve similar performance as [1] but eliminate all floating point operations with limited bandwidth and much better performance than Direct Pixel based Downsampling (DPD) and Pixel-based downsampling with Anti-aliasing Filter (PDAF). We further propose a hardware architecture for our subpixel downsampling method which is highly data re-useable. We are the first few, if not the first, to implement subpixel downsampling method to video by hardware. The design is implemented with TSMC 0.18um CMOS technology and costs 244k gates. At a clock frequency of 63 MHz, the architecture achieves real-time 1920 × 1080 subpixel downsampling at 30fps. © 2011 IEEE.

Motion Estimation (ME) is the most computationally intensive part in the whole video compression process. The ME algorithms can be divided into full search ME (FS) and fast ME (FME). The FS is not suitable for high definition (HD) frame size videos because its relevant high computation load and hard to deal with complex motions in limited search range. A lot of FME algorithms have been proposed which can significantly reduce the computation load compared to FS. Though many kinds of hardware implementations of ME have been proposed, almost all of them fail to consider about the motion vector field (MVF) coherence and rate-distortion (RD) cost which have significant impact to the coding efficiency. In this paper, we propose a hardware friendly ME algorithm and corresponding highly data reusable hardware architecture. Simulation results show that the proposed ME algorithm performs better RD performance than conventional FME algorithm. The proposed reconfigurable ME hardware is implemented in VHDL and mapped to a low cost Xilinx XC3S1500 FPGA. It works at 100MHz and is capable to process 1920 × 1080 of 30fps video format in real time and have very high data reuse ratio. © 2010 IEEE.

Motion Estimation (ME) is the most computationally intensive part in the whole video compression process. The ME algorithms can be divided into full search ME (FS) and fast ME (FME). The FS is not suitable for high definition (HD) frame size videos because its relevant high computation load and hard to deal with complex motions in limited search range. A lot of FME algorithms have been proposed which can significantly reduce the computation load compared to FS. Though many kinds of hardware implementations of ME have been proposed, almost all of them fail to consider about the motion vector field (MVF) coherence and rate-distortion (RD) cost which have significant impact to the coding efficiency. In this paper, we propose a novel hardware-oriented motion estimation algorithm called RD Optimized single-MVP-biased FS (RDOMFS), and corresponding highly data reusable hardware architecture. Simulation results show that the proposed ME algorithm performs better RD performance than conventional FME algorithm. The design is implemented with TSMC 0.13um CMOS technology and costs 103k gates. At a clock frequency of 61 MHz, the architecture achieves real-time 1920 × 1080 RDO-VBSME at 30fps. © 2010 IEEE.

Multiple description coding (MDC) is a source coding technique that exploits path diversity to solve packet losses over error-prone channels. In this paper, we propose an improved drift-free multi-state MDC method based on H.264/AVC coding scheme. At the encoder side, we compress original video into multiple independent H.264 streams with different coding parameters, which can help us to control correlations between the descriptions. At the decoder side, each description is considered as a noisy observation of the original video, and a linear minimum mean square error (LMMSE) based merge algorithm is proposed to combine the descriptions. Experimental results show that the proposed algorithm can achieve better coding efficiency and visual quality than temporary MDC present in [1]. The error resilience ability is also improved by the fact that each frame is coded twice with different parameters. ©2009 IEEE.