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1. Towards DTCO in High Temperature GaN-on-Si Technology: Arithmetic Logic Unit at 300 °C and CAD Framework up to 500 °C

2. Towards DTCO in High Temperature GaN-on-Si Technology: Arithmetic Logic Unit at 300 °C and CAD Framework up to 500 °C

3. A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology

7. A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET

8. 8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS

9. Combining Spatial and Temporal Properties for Improvements in Data Reduction

10. Foresight: Analysis That Matters for Data Reduction

11. Analysis of a Dynamic Queuing Model for Secondary Users in Cognitive Radio Networks

12. Visualization of Uncertainty for Computationally Intensive Simulations Using High Fidelity Emulators

13. An uncertainty-driven approach to vortex analysis using oracle consensus and spatial proximity

14. Uncertainty modeling and error reduction for pathline computation in time-varying flow fields

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