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Physical systems may be carried out in both hardware and software. Hardware is based on implementing appropriate logic functions in FPGA structures connected with a physical layer of cyber-physical systems (CPSs). Effective technology mapping of these functions in FPGA structures is directly connected with logic synthesis. Thus, in the case of CPSs, we can talk about cyber-physical synthesis. The effectiveness of this synthesis is key from the point-of-view of designing CPSs. This paper focuses on the methods aiming at shortening synthesis time of circuits carried out in FPGA circuits. The proposed synthesis methods stem from an original way of a function representation enabling to quick search for appropriate decompositions. This paper presents a series of original methods. They include enabling for a quick relocating of variables between bound and free sets, time effective and multilevel technology mapping of multi-output function, and techniques of quick efficiency assessing of technology mapping taking non-disjoint decomposition into account. The methods are the basis of the algorithms implemented in the author's synthesis tools such as dekBDD and MultiDec. The effectiveness of the proposed methods was proved via experiments. The main contribution of the paper in the area of cyber-physical synthesis is proposing effective methods of carrying out a hardware layer cyber-physical synthesis that uses the FPGA circuits.

Complicated systems are always required to perform different missions each of which may include several phases. Meanwhile, these systems and their components can get exhausted and deteriorated during the operating processes, which drives systems and components into different states. These systems, which is in possession of the characteristics of multiple states and phased missions simultaneously, are called multi-state and phased-mission systems (MS-PMSs). During the last decade, some scholars have made considerable efforts to study the analyzing methods to the reliability of MS-PMSs. However, compared with the independent researches into multi-state systems or phased-mission systems, the achievement of MS-PMSs is still insufficient. Besides, these studies focused on the modeling methods to the MS-PMSs from the system level and the failure behavior was seldom mentioned. In this paper, by extending our previous studies, two accumulating rules of failure mechanism are provided and a revised hierarchical BDD-based method is proposed to model and analyze the reliability of MS-PMSs. Finally, a simplified realistic example is given to illustrate the using of the proposed method.

Software defined networking (SDN) has been proposed for improving network flexibility and programmability by decoupling control plane and data plane of the network. In SDN, the conflicts between rules need to be avoided, while the partitions of the packet headers need to be precomputed from the configuration rules for the network verification tools. Previous researches usually use the trie-based method and the exhaustive searching with BDD expression to partition the equivalent packet classes (ECs). In this letter, we describe PreChecker to dynamically identify the conflicting rules and divide the rules into ECs. The conflicts between rules are defined for the discrimination of intra-switch conflicts. The MTBDD-based algorithm is proposed for effectively partitioning ECs when updating rules. Both analysis and simulations demonstrate the validity and the better performance of the algorithm. [ABSTRACT FROM AUTHOR]

Design of nonvolatile in-memory computing devices has attracted high attention to resistive random access memories (RRAMs). We present a comprehensive approach for the synthesis of resistive in-memory computing circuits using binary decision diagrams, and-inverter graphs, and the recently proposed majority-inverter graphs for logic representation and manipulation. The proposed approach allows to perform parallel computing on a multirow crossbar architecture for the logic representations of the given Boolean functions throughout a level-by-level implementation methodology. It also provides alternative implementations utilizing two different logic operations for each representation, and optimizes them with respect to the number of RRAM devices and operations, addressing area, and delay, respectively. Experiments show that upper bounds of the aforementioned cost metrics for the implementations obtained by our synthesis approach are considerably improved in comparison with the corresponding existing methods in both area and especially latency. [ABSTRACT FROM AUTHOR]

We introduce a new computer-aided design approach based on free binary decision diagrams (FBDDs) for implementing Boolean functions on crossbars using flow-based computing. Our crossbar synthesis procedure uses generalized FBDDs to design crossbars for a Boolean formula such that there is a flow of current from an input nanowire to an output nanowire through the sneak paths in the crossbar if and only if the Boolean formula evaluates to true. Generalized FBDDs are more succinct representations of Boolean formulas than traditional reduced ordered binary decision diagrams (ROBDDs) because they do not require the same variable ordering along all paths of the decision diagram. Our experimental results with the middle bit of a multiplier show that our designs are 69.9% more succinct than flow-based crossbar computing approaches designed using ROBDDs. [ABSTRACT FROM PUBLISHER]

The software engineering discipline that allows to develop methods and processes that ensure success in building software products, consequently is relevant to instantiate these practices in the development of educational content for t-learning, enabling the development and supply of educational content for digital television. This article proposes a model "MADCE-TVD - Agile Development Model of Educational Content to Digital Television" This is based on the methodologies, agile values and principles. This research is part of the "model of good practice for the development of educational content for T-learning". [ABSTRACT FROM PUBLISHER]

The spare allocation problem in redundant RAM is to replace faulty rows/columns of memory cells with spare rows/columns. To solve the problem, comparison-based search tree structures were used in traditional exact algorithms. These algorithms are not efficient for large problems because significant amounts of data have to be retained and copied in order to generate new partial solutions. Many data may need to be compared for the removal of each redundant partial solution. To overcome these drawbacks, an efficient algorithm is proposed in this paper. The algorithm transforms a spare allocation problem into Boolean functions, and the renowned BDD is used to manipulate them. Experimental results indicate that the proposed algorithm is very efficient in terms of speed and memory requirements. It may also be useful for problems which can be modeled as constraint bipartite vertex cover problems. [ABSTRACT FROM AUTHOR]

The article discusses a new approach that successfully finds the optimal variable orderings for almost all reduced ordered binary decision diagrams (BDD) in the LGSynth91 benchmark circuits. The progress of the approach is attributable to the concept of randomized algorithms which reduce the influence of the initial variable ordering on the minimization performance. For conventional BDD minimization algorithms, the initial variable ordering severely affects the performance.

The traditional problem in binary decision diagrams (BDDs) has been to minimize the number of nodes since this reduces the memory needed to store the BDD. Recently, a new problem has emerged: minimizing the average path length (APL). APL is a measure of the time needed to evaluate the function by applying a sequence of variable values. It is of special significance when BDDs are used in simulation and design verification. A main result of this paper is that the ARL for benchmark functions is typically much smaller than for random functions. That is, for the set of all functions, we show that the average APL is close to the maximum path length, whereas benchmark functions show a remarkably small APL. Surprisingly, however, typical functions do not achieve the absolute maximum APL. We show that the parity functions are unique in having that distinction. We show that the APL of a BDD can vary considerably with variable ordering. We derive the APL for various functions, including the AND, OR, threshold, Achilles' heel, and certain arithmetic functions. We show that the unate cascade functions uniquely achieve the absolute minimum APL. [ABSTRACT FROM AUTHOR]

We have been investigating a design methodology of SFQ logic circuits based on the binary decision diagram (BDD). In the previously proposed BDD SFQ logic circuits, we have used one-to-two binary switches as a node cell in a BDD tree. In this study we will propose a new implementation method of SFQ BDD circuits, in which two nodes are implemented by using a 2-input 2-output switch gate. By employing the new approach, we have designed and implemented a one-bit full adder using the NEC 2.5 kA/cm² Nb standard process and the CONNECT cell library. The maximum operating frequency of the full adder was found to be 40 GHz by circuit simulations and 32.8 GHz by on-chip high- speed tests. [ABSTRACT FROM AUTHOR]

We introduce a new BDD-like data structure called Hybrid-Restriction Diagrams (HRDs) for the representation and manipulation of linear hybrid automata (LHA) state-spaces and present algorithms for weakest precondition calculations. This permits us to reason about the valuations of parameters that make safety properties satisfied. Advantages of our approach include the ability to represent discrete state information and concave polyhedra in a unified scheme, as well as to save both memory consumptions and manipulation times when processing the same substructures in state-space representations. Our experimental results document its efficiency in practice. [ABSTRACT FROM AUTHOR]

The recent literature showed that, in many cases, Ordered Binary Decision Diagram (OBDD)-based algorithms are more efficient in reliability evaluation compared to other methods such as the Inclusion-Exclusion (I-E) method and the sum of disjoint products (SDP) method. This paper presents algorithms based on OBDD to compute system failure frequencies and reliability importance measures. Methods are presented to calculate both steady-state and time-specific frequencies of system-failure as well as system-success. The reliability importance measures discussed in this paper include the Birnbaum importance, the Criticality importance, and other indices for the risk evaluation of a system. In addition, we propose an efficient approach based on OBDD to evaluate the reliability of a nonrepairable system and the availability of a repairable system with imperfect fault-coverage mechanisms. The powerful capability of OBDD for reliability evaluation is fully exploited in this paper. Further, we extend all of the proposed algorithms in this paper to analyze systems with imperfect fault-coverage. [ABSTRACT FROM AUTHOR]