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This brief presents the on-chip background offset and timing-skew calibration of the 1-then-2b/cycle time-interleaved successive-approximation-register analog-to-digital converter (TI SAR ADC). For timing-skew between sub-ADC’s sampling clocks, a comparator offset-based window detector (WD) is used to adjust the clock edge misalignment. In addition, comparator offset calibration is considered both in terms of 1) global offset (between the offset-free reference comparator and the local reference comparator in each sub-ADC) and 2) local offset (between the local reference comparator and the rest of the comparators in the same sub-ADC). The proposed calibration sufficiently suppresses noise floor and spurs, and all calibrations are performed in the background without interfering with normal ADC operation. The prototype 5-way TI SAR ADC is fabricated in a 28 nm CMOS process and occupies a 0.03 mm2 area including on-chip calibration. With the proposed calibration, the prototype achieves SNDR of 40 dB at Nyquist input and consumes 7.57 mW, leading to the Walden figure of merit (${\text {FoM}_{W}}$) of 37.2 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

This article proposes a 3.2-GHz subsampling phase-locked loop (SSPLL)-based injection-locked clock multiplier (ILCM) using a subsampling delay-locked loop (SSDLL). The proposed ILCM achieves a superior noise reduction effect at low offset frequency because of the high feedback gain of SSPLL. Also, SSDLL is proposed for background phase calibration between SSPLL and injection. Since SSPLL and SSDLL use identical SSCP, the power consumption of the frequency and phase calibration is only 1.32 mW. This work is fabricated in a 65-nm CMOS process, and the 10-kHz phase noise is improved by 8.6 dB. The rms jitter from 10 kHz to 30 MHz is 178 fs. The chip-to-chip variations (20 chips) are 17 and 169 fs with/without SSDLL, respectively. The measured results show that FoM1, FoM2, and total power consumption are −245.1, −260.1 dB, and 9.85 mW, respectively. [ABSTRACT FROM AUTHOR]

This brief presents a low-power asynchronous 10-bit 2-then-1b/cycle successive approximation register (SAR) analog-to-digital converter (ADC). With partial adoption of 2b/cycle mode only for higher-order bit conversions, additional area and power consumption could be minimized while maintaining fast conversion rate. Moreover, unlike the previous 2b/cycle conversion architecture, where two capacitive digital-to-analog converters (C-DACs) and multiple analog comparators are unavoidable, the proposed 2-then-1b/cycle conversion is implemented with only one C-DAC and one analog comparator by utilizing a digital-based time-domain reference. The speed of 1b/cycle conversion for lower-order bits is improved with a dual-mode comparator. With the aforementioned techniques, the prototype 10-bit SAR ADC is fabricated in 65 nm CMOS process. The ADC core occupies an active area of 0.0142 mm2 and consumes power of 3.8 $\boldsymbol{\mu }\text{W}$ at 0.5 V supply voltage and 3 MS/s conversion rate. The SNDR measured at a Nyquist-rate input frequency is 56.41 dB, resulting in a figure of merit (FoM) is 2.33 fJ/c.-s. [ABSTRACT FROM AUTHOR]

Gesture recognition has increasingly become one of the most popular human–machine interaction techniques for smart devices. Existing gesture recognition systems suffer from either excessive power consumption or large size, limiting their applications for ultralow-power wearable devices. This article presents an accurate area-efficient and low-power real-time gesture recognition system for smart wearable devices. The proposed work utilizes an accurate peak-based gesture classification engine with less memory and a low-resolution and low-power on-chip image sensor for achieving high area efficiency and low power. In addition, the feature extraction architecture removes fixed-pattern noises from the low-power on-chip image sensor for accuracy improvement and employs parallelism for recognition speed enhancement. Thus, the proposed system accomplishes accurate real-time gesture recognition for eight motion hand gestures with an average recognition accuracy of 90.6% and latency of 4.228 ms. Measurement results of a test chip fabricated in 65-nm CMOS demonstrate that the proposed system consumes $137.0~\mu \text{W}$ at 30 frames/s while occupying only 1.78 mm2, which achieves the lowest power and smallest area among the recently reported gesture recognition systems. [ABSTRACT FROM AUTHOR]

A single-inductor multiple-output (SIMO) dc–dc converter with output-voltage-aware charge control (OVACC) is presented in this paper. The OVACC scheme reduces the cross regulation by computing the total energy required by all outputs to extract exactly the same amount of energy from the input. Moreover, the proposed design also extends the load capability range of the SIMO converter by supporting the operation in both continuous conduction mode and discontinuous conduction mode while boosting the overall power efficiency. The proposed SIMO (five outputs) dc–dc converter has been implemented in a 0.18 μm 1P6M CMOS process. Measurement results show that the best cross regulation is 0.016 mV/mA when the output current of 250 mA abruptly changes. And no cross regulation is observed when the first output current changes 150 mA, the second output current changes 160 mA, the third and fourth output currents change 180 mA, and the last output current changes 250 mA. Also, the measured peak power efficiency is 86%. [ABSTRACT FROM AUTHOR]

This paper proposes an analog front-end (AFE) IC using a multiple-frequency driving method (MFDM). The proposed AFE IC achieves a high signal-to-noise ratio (SNR) by using an external noise spectrum and locating the frequencies of the excitation signals in low-noise regions. In addition, it employs the MFDM to increase the frame rate by simultaneously sending excitation signals having multiple frequencies to the touch screen panel (TSP). The proposed AFE IC extracts the coordinates of the finger as well as the coordinates, pressure, and tilt angle of the active stylus with the force gauge and gyro sensor. The proposed AFE IC and active stylus were fabricated in a 0.13- \mu \textm standard CMOS process. The measurement results show that the proposed AFE IC achieves a frame rate of 3.9 kHz, and SNRs of 61.0 and 50.1 dB when a finger and active stylus are used, respectively. In addition, the pressure and tilt angle of the active stylus are expressed with 6-bit resolution. A capacitive touch system with the proposed AFE IC is demonstrated with a 65-in $104\times 64$ TSP using ten fingers and the active stylus with the pressure and tilt angle. [ABSTRACT FROM AUTHOR]

This paper presents a direct digital frequency synthesizer (DDFS) based on the nonlinear DAC with a maximum operating frequency of 2 GHz. This work proposes three design methods to enhance the performance of a DDFS. First, a multi-level momentarily activated bias is proposed to reduce power dissipation in the phase accumulator. Second, a coarse phase-based consecutive fine amplitude grouping scheme is presented to reduce hardware complexity and power consumption in the digital decoder. Third, the mixed-wave conversion topology in the nonlinear DAC is proposed to improve the output spectral purity. The DDFS with 9 bit amplitude resolution is capable of producing a minimum spurious-free dynamic range (SFDR) of 55.1 dBc up to Nyquist frequency at the clock frequency of 2 GHz. The prototype DDFS is fabricated in a 55-nm CMOS. It occupies an active area of 0.1 mm 2 with a total power dissipation of 130 mW. The figure of merit of this DDFS is 8944 GHz · 2 (SFDR/6) /W. [ABSTRACT FROM AUTHOR]

This article discusses the challenges, benefits and approaches associated with realizing largescale antenna arrays at mmWave frequency bands for future 5G cellular devices. Key design considerations are investigated to deduce a novel and practical phased array antenna solution operating at 28 GHz with near spherical coverage. The approach is further evolved into a first-of- a-kind cellular phone prototype equipped with mmWave 5G antenna arrays consisting of a total of 32 low-profile antenna elements. Indoor measurements are carried out using the presented prototype to characterize the proposed mmWave antenna system using 16-QAM modulated signals with 27.925 GHz carrier frequency. The biological implications due to the absorbed electromagnetic waves when using mmWave cellular devices are studied and compared in detail with those of 3/4G cellular devices. [ABSTRACT FROM PUBLISHER]

A novel antenna module solution which dramatically alleviates cost and fabrication related limitations of traditional 60-GHz antenna modules is demonstrated. The antenna topology is wholly devised using industry standard FR-4 PCB and is integrated into the 60-GHz transceiver carrier board. As a result, the proposed approach effectively bypasses the need for any complicated grid array assemblies for the first time to the author's best knowledge. The antenna element is first designed and confirmed to exhibit more than 9-GHz bandwidth and 71% average radiation efficiency from 57–66 GHz. The design is further expanded into an 8-element phased array module and integrated with a 60-GHz RFIC transceiver and digital interface. The overall footprint of the antenna module within the carrier board is 20\,\times\,20\,\times\, 0.838 mm^3 . System-level evaluation confirms the 8-element phased array module to be highly sufficient in scan range, side lobe levels and radiation efficiency for 60-GHz wireless systems, particularly in the field of consumer electronics. [ABSTRACT FROM AUTHOR]

This paper demonstrates the possibility and feasibility of an ultralow-cost antenna-in-package (AiP) solution for the upcoming generation of wireless local area networks (WLANs) denoted as IEEE802.11ad. The iterative design procedure focuses on maximally alleviating the inherent disadvantages of high-volume FR4 process at 60 GHz such as its relatively high material loss and fabrication restrictions. Within the planar antenna package, the antenna element, vertical transition, antenna feedline, and low- and high-speed interfaces are allocated in a vertical schematic. A circular stacked patch antenna renders the antenna package to exhibit 10-dB return loss bandwidth from 57–66 GHz. An embedded coplanar waveguide (CPW) topology is adopted for the antenna feedline and features less than 0.24 dB/mm in unit loss, which is extracted from measured parametric studies. The fabricated single antenna package is 9 mm\,\times\,6 mm\,\times\,0.404 mm in dimension. A multiple-element antenna package is fabricated, and its feasibility for future phase array applications is studied. Far-field radiation measurement using an inhouse radio-frequency (RF) probe station validates the single-antenna package to exhibit more than 4.1–dBi gain and 76% radiation efficiency. [ABSTRACT FROM PUBLISHER]

This paper presents a power-efficient fully digital amplifier (FDA) with low-power consumption for portable audio systems. Input dependent bit flipping (IDBF) technique is proposed and employed in the FDA to reduce the switching rate of the 1-bit delta-sigma modulator (DSM) compared to conventional 1-bit DSM-based FDAs, thus lowering pulse repetition frequency (PRF). Experimental results verified on FPGA demonstrate that the PRF with IDBF is the range between 426 KHz and 466 KHz depending on input amplitude, whereas the PRF without IDBF is the range between 722 KHz and 1020 KHz. Therefore, the proposed amplifier significantly improves power efficiency without serious degradation of the signal-to-noise ratio (SNR)1. [ABSTRACT FROM AUTHOR]

This paper presents a Mobile Display Digital Interface (MDDI)-client architecture which is suitable for low-power, small-area, and low-cost mobile applications. Compared to the power dissipation of an MDDI client with a byte counter that has continuous transitions for all packet data, the proposed MDDI client reduces power consumption in state transitions up to 50% by using robust Finite State Machine (FSM) and on-off byte counter. The proposed scheme detects invalid data in packets and turns off the operation of the byte counter to minimize client's power dissipation. The MDDI-client architecture is implemented and verified on FPGA modules. [ABSTRACT FROM PUBLISHER]

In this paper, we present a multi-lane Mobile Industry Processor Interface (MIPI) Camera Serial Interface (CSI) receiver which is suitable for high-resolution camera and High-Density (HD) video applications. The presented receiver is designed to achieve parallel processing so that it reduces dynamic power consumption for multi-lane configuration. In order to facilitate parallel processing, we propose two techniques for the multi-lane receiver. The presented design receives data at the maximum rate of 4Gb/s and is verified in a standard CMOS technology. [ABSTRACT FROM PUBLISHER]