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Digital signal processing (DSP) subject is one of the most important core subjects in many disciplines of electronic engineering, while the digital FIR filters are one of the essential topics of DSP. Students at their early stages of university study require clear understanding of digital filters basics in both theoretical and practical work. This paper concentrates on how to make it easy for a student to understand the theory behind FIR filters by implementing the filters in practical laboratory work. The work comprises the use of MATLAB Filter Design and Analysis Tool (FDAT) to obtain the desired filter coefficients, then using the open-source Arduino Due microcontroller to implement the FIR filter function in software. The filter coefficients, which are obtained from MATLAB FDAT are truncated to be accepted by Arduino software as a single line of software. Using the ADC and the DAC available in Arduino, the FIR filter analog input and output can be both observed and analyzed by the student to verify the designed filter characteristics. A real time FIR filter (with an order of 10) was realized in Arduino software using signal frequencies less than 5KHz.

Pseudo Noise (PN) code is one of the most well-known codes for spreading and secure information in Wireless Communication Systems (WCS) and recently for estimating the carrier and the frame timing information for advanced multipath resistive OFDM systems. Synchronization, with its two steps (acquisition and tracking), is a challenging task for such Multiple Access Systems (MAS). In this paper a Novel Fast Clocking Acquisition Synchronizer (NFCAS) which is based on parallel code phases comparison is designed, modeled, simulated and practically implemented using Field Programmable Gate Array (FPGA). In the proposed synchronizer a fast clock is introduced to speed up the synchronization process. The synchronizer shows a very fast, reliable and direct synchronization in one step rather than two steps. Also the simulation and practical results show a perfect consistency for codes synchronization time which is inversely proportional to the ratio between the introduced fast acquisition clock and the common (transmitter/receiver) traditional slow clock.

Direct identification and subsequent replacement of faulty components in electronic circuits reduces the overall maintenance costs and time-to-repair the items. In this paper, a tool that can identify the faulty component in any position in the circuit has been designed, simulated and implemented. Device software use wavelet transform algorithm to recognize the signature of the faulty component. The circuit is broken down to its sub-circuits that each one has a stimuli point and tests nodes, so that each component within the sub-circuit response by a distinguishable signature among other component of the same sub-circuit when it fails. The system was tested and a high level of fault detection was recorded.

High permeable concrete (HPC), due to its high void ratio and permeability, is considered as an option to substitute the conventional impervious pavements for managing stormwater runoff in a cost-effective and friendly environmental way. HPC is made of single graded sized of coarse aggregate bound together with ordinary cement without or with little fine aggregate. Due to its low compressive strength, HPC is only used as pavement material. For the purpose of developing a new type of HPC with enhanced structural strength without compromising its permeability, five pozzolanic materials (fly ash, silica fume, papermill ash, palm oil ash and rice husk ash) were used as partial replacement to ordinary cement. Their effects on the compressive strength, void ratio and permeability of HPC were investigated. It was found that 5% of cement replacement with pozzolan will lead to enhance the compressive strength and permeability of HPC.

A precast, prestressed concrete girder with circular web openings allows building service systems (mechanical, electrical, communications, and plumbing) to cross the girder line within the member’s depth, reducing a building’s floor -to-floor height and the overall height of the structure. These height reductions have the potential to improve the competitiveness of total precast concrete structures versus other types of building systems. The experimental program reported in this paper tested three inverted -tee girders with circular web openings strengthened with GFRP to failure to evaluate the openings’ effect on girder behavior. The test girders were designed using available recommendations in the existing literature. Finite element is used to plot interaction diagram in estimating the cracking load for the different crack patterns was perform. Good agreement was shown between the interaction diagram and the experimental results.