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We report here preliminary results on a new Cu-cored flip chip structure combining C4NP (Controlled Collapse Chip Connect New Process) with Cu spheres for high density interconnections. C4NP is a new wafer bumping technology developed by IBM in which molten solder is injected into a mold and then transferred to the UBM (Under Bump Metallurgy) pads on the wafer. This simple and parallel process has shown the capability to combine low cost attributes with high performance capabilities. C4NP allows a larger number of interconnections with finer pitch than screen printing methods because it eliminates the volume reduction problem of solder paste. Also, C4NP allows more freedom in selecting the composition of solder bumps when compared with the electroplating method. To make Cu-cored flip chip interconnections with C4NP, Cu spheres are arrayed in the cavities on a mold which matches the CTE of the wafer. The Cu spheres are then transferred from the Si mold to C4NP solder bumps on the wafer by using the same process used for C4NP solder transfer. Then, after dicing, the diced chip is flip chip assembled on the substrate which has been pre-soldered. This combination of C4NP and Cu spheres is a dry process with potential for low cost, because it does not need thick photoresist, lithography, or plating process steps. Our early laboratory demonstrations of Cu-cored bumping have processed individual chips rather than full wafers; but, based on our manufacturing experience with C4NP solder bumping, we expect the process to be readily extendible to wafer scale. The C4NP Cu-cored flip chip joints offer potential advantages in stress mitigation and electrical performance. The centered Cu sphere in the joint ensures greater stand-off for fine pitch, which facilitates the underfill process and improves fatigue resistance due to the taller bump. The low electrical resistivity of Cu enhances current carrying capacity. The small Sn/Cu ratio in the bump would decrease UBM consumption and solder depletion under high current stressing. The high thermal conductivity of Cu also enhances heat transfer from the chip to the substrate. Due to the high Cu/Sn ratio in the flip chip interconnections, the higher Young's modulus of Cu over solder could be a concern for stress concentration on the IC despite the higher stand-off height provided by the Cu-core bump. However, in the C4NP Cu-cored flip chip structure, since the transfer mold is used for inserting Cu spheres into the flip chip joints, Cu spheres can be selectively deployed only to the joints where the composite bumps are required, whereas the other, highly stressed joints can be electrically connected without Cu spheres. Therefore, the selective use of composite interconnects may allow stress to be minimized while optimizing electrical performance.

Controlled collapse chip connection new process (C4NP) is currently used in IBM manufacturing for all 300 mm Pb-free wafer bumping for flip chip packages. In this study, the extendibility of C4NP technology to ultra fine pitch applications has been explored. Reusable C4NP glass molds were fabricated and characterized for 50 mum pitch application. Mold fill and wafer transfer with Pb-free solders have been demonstrated using both 200 mm and 300 mm wafers in a manufacturing environment. Significant improvement in bump yield was achieved for these early demonstrations of fine pitch interconnections through process optimization and contamination control. Challenge in wafer inspection metrology is discussed for the 50 mum pitch micro-bumps. Mechanical strength of the C4NP micro-bumps has been characterized using test dies with a full area array of micro-bumps.

Technology roadmaps for electronic packaging and 3D integration show the continuing trend of increasing input/output connection density between the semiconductor chip and the package or between two different IC's. For FlipChip packaging applications, 150 mum pitch full grid solder bump arrays have already entered production. Bump pitch requirements for 3D applications such as the integration of memory and logic are even tighter. These fine pitch applications exceed the capabilities of traditional wafer bumping processes such as solder screening or ball placement. Controlled Collapse Chip Connection - New Process (C4NP) technology has the ability to produce these very fine pitch connections in a cost effective manner. This paper reviews the latest C4NP data for a 50 mum pitch application. Glass molds were fabricated, filled with solder, inspected, and the solder transferred to a fine pitch wafer. Four molds have been fabricated with cavity top diameters ranging from ~33 to 40 mum., The molds were filled with binary SnAg solder using the mold fill tool, automatically inspected with the mold inspect tool, and wafers were bumped with the solder transfer tool. Characterization of the filled molds and bumped wafers is presented. In addition, the paper also reviews production cost analysis for various UBM stackups and solder bump processes, based on a specifically developed cost model. The Electroless Ni Immersion Au (ENIG) UBM structures in combination with C4NP solder bumping provide a significant cost reduction over alternative structures. C4NP is a unique solder bumping technology developed by IBM which addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. It is a solder transfer technology where molten solder is injected into pre-fabricated and reusable glass molds. The glass mold contains etched cavities which mirror the bump pattern on the wafer. The filled mold is inspected prior to solder transfer to the wafer to ensure high final yields. Filled mold and wafer are brought into close proximity/soft contact at reflow temperature and solder bumps are transferred onto the entire 300 mm (or smaller) wafer in a single process step without the complexities associated with liquid flux. C4NP technology is capable of fine pitch bumping while offering the same alloy selection flexibility as solder paste printing. The simplicity of the process makes it a low cost, high yield and fast cycle time solution for both, fine-pitch as well as chip scale package bumping applications. Fine pitch C4NP molds were fabricated by ULCOAT, Japan. Mold fill, inspect and solder transfer was done using the C4NP process at the IBM Hudson Valley Research Park, Hopewell Junction, New York, United States.

In the past, traditional CMOS scaling has been one of the principal levers to achieve increased system-level performance. Today, scaling is becoming increasingly difficult and less effective, and a range of new two- and three-dimensional silicon integration technologies are needed to support next-generation systems. A silicon-carrier system-on-package (SOP) is an advanced packaging solution, enabling interconnection between ICs and other devices at densities far beyond those of current first-level packaging. Silicon-carrier employs fine pitch Cu damascene wiring, high-density solder pads/joins and high-yielding electrical through-vias. A novel approach to fabricating robust though-vias in silicon is described. The key design feature enabling large-area, uniform arrays to be produced with high yield is the annular via shape. As compared to a standard cylindrical via shape, the annular via is easier to integrate into a standard CMOS copper back-end-of-the-line (BEOL) process flow. Two process flows are compared: the first having the conductor metal within the gap of the insulated annulus itself, the second having a conducting metal core enclosed within the inner wall of the annulus. For the first process flow, two annular conductors, plated copper and CVD tungsten, are compared in terms of ease of integration, yield and susceptibility to failure during thermal stressing. Large area (45 /spl times/ 48 mm) silicon carrier modules containing more than 51,000 electrically measurable through-vias are used to compare overall yield and robustness of each process. Results on deep thermal cycling, current carrying capacity and thermomechanical modeling are discussed. Wafer-level via testing is used to statistically distinguish between via chain opens caused by bond and assembly issues versus failures in the vias or integrated wiring structures. Through-via resistances on the order of /spl sim/10 m/spl Omega/ are typical, and through-via yields of 99.98% at module level have been demonstrated.

This paper describes yield, contact resistance, and preliminary reliability test results on micro-bump C4 interconnects in modules containing Si-chips and Si-carriers. Modules containing eutectic PbSn or SnCu bump solders were fabricated with high yield, with similar interconnect contact resistances for both solders. The contact resistance and reliability test results to date suggest that reliable, high-current, high-density bump interconnections can be achieved for Si-carrier technology.

A silicon-based system-on-package (SOP) is described. Novel capabilities of SOP are expected to enable lower cost, more efficient and higher performance electronic systems. Newly developed technology elements include: electrical silicon through-vias, fine-pitch, high bandwidth wiring, fine pitch solder interconnection, fine pitch known-good-die, and advanced microchannel cooling. Applications may range from miniaturized consumer products such as integrated function cell phones to high performance computers. SOP technology and related chip stacking challenges have been investigated and robust technology options are reported. Silicon through-vias can be fabricated using copper, tungsten, composite or alternate conductors. Via design and structure are discussed for vias in thin silicon packages mounted on a supporting substrate as well as thick silicon package that can be handled without a supporting substrate. Fine-pitch, high bandwidth wiring has been fabricated, characterized and shows greatest bandwidth for shorter interconnection distances. Fine pitch area array solder interconnections have been fabricated and characterized electrically, mechanically and with accelerated reliability testing. These fine pitch interconnections can enable the high bandwidth wiring for chip-to-chip interconnection. Integrated decoupling capacitors have been fabricated using parallel plate and trench technology. The integrated decoupling capacitors can provide under-chip, low inductance bypassing to minimize noise from simultaneous switching noise. New fine pitch, area array test technology provides a path to wafer level test for known-good-die, functional test, and burn-in for the fine pitch chip I/O. Advanced microchannel cooling can be leveraged to support high power, close proximity chips and chip stacks for cooling > 300 W/cm/sup 2/. This IBM research paper describes the design, technical challenges and progress for next generation SOP technology, chip stacking, characterization, and potential new applications.

To support the next generation highly integrated microsystem with 3D silicon integration using fine pitch interconnection and Si carrier, we develop a fabrication and assembly process at IBM Research to produce solder micro-joints (fine pitch flip-chip interconnections) for our system-on-package (SOP) technology. We fabricate solder bumps with 25 /spl mu/m (or less) in diameter on 50 /spl mu/m pitch size, as well as 50 /spl mu/m in diameter on 100 /spl mu/m pitch size, at wafer level (200mm) by electroplating method. There are up to 10208 micro-bumps (25 /spl mu/m) built on a chip surface less than 0.4 cm/sup 2/. The process can be applied to various solder compositions, including eutectic SnPb, Pb-free (CuSn), AuSn and high Pb (3Sn97Pb) solders. The test matrix includes different solder/UBM (under bump metallization) combination. In this paper, the discussion focuses on the fabrication, assembly and characterization of the micro-joints made with of Pb-free (CuSn) and eutectic SnPb solders with Ni and/or Cu stack plating. The preliminary electrical and mechanical test results indicated that reliable and high yield micro-bumps can be successfully made with this fabrication and assembly process.

System-on-chip (SOC) and system-on-package (SOP) technologies each have advantages depending on application needs. As system architects and designers leverage ever-increasing CMOS technology densities, a range of two and three dimensional silicon integration technologies are emerging which likely support next generation high-volume electronic applications and may serve high-performance computing applications. This paper discusses a few emerging technologies which offer opportunities for circuit integration on-chip as well as on-package using fine pitch interconnection, silicon wafer processing and silicon carrier packaging technology. Advanced silicon carrier package technology with fine pitch (50/spl mu/m) interconnection is described. This silicon carrier package contains silicon through-vias and offers >16/spl times/ increase over standard chip I/O, a 20/spl times/ to 100/spl times/ increase in wiring density over traditional organic and ceramic packaging, and allows for integrated high performance passives. Silicon carrier technology supports lithographic scaling and provides a basis for known good die (KGD) wafer testing. It may be considered for use in a number of applications including optoelectronic (OE) transceivers and mini-multi-chip modules (MMCM) which integrate heterogeneous dies forming a single "virtual chip".

The design, fabrication, assembly and characterization of a novel silicon carrier package used for enabling a Tb/s parallel optical transceiver is reported. Electrical through-vias, high speed wiring and a through cavity for housing optoelectronic (OE) devices are critical features of the silicon carrier that allow high density integration of optical and electrical components on a single substrate, resulting in a small form factor system that is capable of meeting high bandwidth requirements of large computing systems. A novel hierarchical approach involving eutectic AuSn and SnPb solder systems and flip chip bonding technology is used to assemble the transceiver module. The optical system used for coupling light from the OE devices to waveguides is based on a relay lens that is integrated into the OE array. The measurement and model for alignment tolerance analysis showed constant coupling efficiency from the OE to waveguide over a range of plusmn 10 mum, giving an excellent margin for alignment. Electrical simulations and measurement of silicon carrier through-vias showed an insertion loss of better than 1 dB at 20 GHz. Simulations and measurements also exhibited an attenuation of 4.3 dB/cm at 20 GHz for high speed wiring on the silicon carrier, which was adequate for 20 Gbps data transmission over a channel length of 7 mm

This paper describes the successful concurrent fabrication of micro-electro-mechanical (MEM) electrostatic switches and resonators on the same wafer. Base processes from copper interconnect technology were used to fabricate devices allowing for easy introduction of MEMS technology into CMOS IC manufacturing. Both switches and resonators were electrically tested in a controlled ambient to determine performance and characteristics.

This paper summarizes the adhesion test standard and technique developed collectively by groups from the IBM Research Division, Yorktown Heights, and the Development Laboratory of IBM Microelectronics Division at East Fishkill. This activity was Initiated since the increased complexity of interconnection technologies require a large number of interfaces to maintain their integrity while being subjected to a large variety of processes. For example, reliable adhesion of polymer layers to metals and ceramics plays a vital role in several IBM key product technologies, such as the recently announced Glass-Ceramic Module multichip packaging technology used in the system 390/ES9000, models 820, 900 and 9021, computers and the Metallized Ceramic Polyimide (MCP) products. During the course of these product development cycles, it was noted that, sample preparation and measurement techniques can strongly affect the measured adhesion strength of a multi-component structure such as that found in multichip and multilayer modules. As a result of the observed variability in a multitude of adhesion measurements from many IBM laboratories, it was decided that standardization of the sample preparation and adhesion measurement techniques was required. During the course of collective work between a large number of participants, it became clear, that once a certain number of rules are followed, data collected from different workers can be compared. These rules form the basis of the peel standard which is discussed here. Once the standard measurement of adhesion is implemented, various adhesion promotion techniques can be directly compared, which lead to a swift and facile improvement in the reliability of products and in their development cycle time.

As mobile computing and telecommunication electronics are spreading fast, a demand for microelectronics packaging schemes for high density, fine pitch, high performance and low cost becomes even more severe. Specifically, the conventional printed circuit board (PCB) with plated-through-hole (PTH) vias is difficult to justify its manufacturing cost as well as the packaging density requirement. To meet this challenge, several new manufacturing schemes of high density and high performance PCB have been recently introduced such as surface laminar circuit (SLC), array layer inner via hole (ALIVH) and others. This new PCB fabrication process is categorized as sequential build-up (SBU) or build-up multilayer (BUM) using laminate-based substrates, where via holes are filled with a conductive paste material to make reliable vertical or Z-interconnects. In this paper, a new electrically conducting paste material to be used for via filling is introduced. The new conducting material consists of a conducting filler powder coated with a low melting point metal or alloy, a mixture of several thermoset resins, and other minor organic additives. By varying the filler content and resin chemistry, several formulations have been produced to fill via holes with a high aspect ratio. Via fill experiments have been performed to demonstrate void-free microstructure with good electrical continuity. Various bulk properties such as thermal, electrical and mechanical have also been characterized to understand the material behavior during via filling as well as the field service.

We describe a liner for Cu-Damascene multilevel ULSI interconnects, which satisfies all the important requirements for a high performance and reliable Cu interconnect technology. This liner is implemented in the first manufacturing process to produce and ship CMOS chips with Cu interconnects. The liner is a bilayer from a family of hcp/bcc-TaN followed by bcc-Ta (/spl alpha/-Ta), deposited sequentially in a single PVD chamber from a pure Ta target, using Ar and N/sub 2/ sputtering gases. This bilayer simultaneously maximizes adhesion to the interlevel dielectric and the Cu fill, and has very low in-plane resistivity (/spl sim/30-60 /spl mu//spl Omega/-cm, depending on TaN/Ta thicknesses). These qualities produce high-yield, highly reliable, and electromigration-redundant Cu interconnects.