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Major disease causing micro-organisms are bacteria and viruses, which are not visible when it affects the plant at initial stage. The human naked eyes after only the later stage it’s visible and its affected whole parts of plants. Artificial Intelligence is an emerging sector in all fields of works for automation and to improve efficiency. It also included in agricultural sector to improve crop yield by identify the disease affection at early and classify type of disease affected for taking precaution measurements to prevent spreading to other plants in field. This becomes possible by image processing on computer vision and train the model by using VGG-16 architecture which is Convolutional Neural Network algorithms.

Medical image segmentation is a bottleneck for physicians and radiologists in diagnosis of diseases. Deep learning based convolutional neural networks (CNNs) is used to support decision making in medical diagnosis. Three architectures are analyzed for segmentation of affected tissues. CNN with contraction path classifies the each pixel in the image into region of interest and region of non interest. The affected region is then segmented from RoI. Second architecture is developed with contraction and expansion paths (auto-encoders) to extract the spatial information of the pixels from the input image. The deconvolutional layer extracts the spatial information related to corresponding features but still fails to capture contextual dependent information of high-level features. In the third architecture, attention module with U-Net captures the contextual dependent information. Filter size, learning rate and k-fold cross validation are tuned to improve the accuracy and dice similarity coefficient (DSC). Filter size and k-fold cross validation are varied as 3x3, 5x5 and 7x7 and 3-fold, 5-fold and 10-fold respectively. The attention module helps to extract the spatial information of the high level features which are related to low level features. This gives better segmentation output. U-Net with attention module provides an accuracy 99.07 %, sensitivity 98.57 %, specificity 99.5 % and DSC 91.7%.

Segmentation is one of the important and challenging tasks in medical image analysis. Region of Interest (RoI) needs to be segmented from the background in almost all types of medical images for further analysis. This assist doctors in perfect diagnosis of diseases. In this paper convolutional neural network (CNN) has been used for automatic segmentation of RoI in medical imaging modalities such as carotid artery ultrasound images. The results obtained through proposed CNN are compared with other machine learning algorithm such as support vector machine (SVM) and radial basis function (RBF). CNN exhibits an edge in performance with 10-fold cross validation over the other two networks with an accuracy of 99.3%. The results are also compared with other standard CNN architectures.

Now-a-days, Internet of Things (IoT) develops a huge need for industry automation. It contributes machine learning and machine-to-machine communication which enables sophisticated monitoring and control of industrial process. A set of sensors and actuators are connected to a process machine called node device. The node devices simply collect the sensor data and send those data to cloud directly or through internet gateway. If the process machine or process method is changed, the node device and also should respond to fit in the new process mechanism. Even a small sensor changes lead to change in process mechanism which results more cost in upgrading the node device. To overcome these issues, an innovative re-configurable node device is proposed. Reconfigurable nodes have a special feature of customizable firmware. Here, the control algorithm of the Reconfigurable node device can be modified based on application needs. It also customizes the sensor interface routines, sensor data calibration and calculations. Process mechanism can be modified by these customized features of Reconfigurable node device. The Reconfigurable nodes help reduce the implementation cost of IoT in industrial process and makes easy to upgrade at any time.

India is a country of diversity with different religious views containing 7 crores of people. Most of our country devotees pay their loyal towards lord by offering money, donating jewels and other materials depending upon their economical status. Most of them preferred their donation in the form of money. Hundi is the devotee donating containers in the temples. We proposed to develop an automatic coin and currency counter in the temple to count the total amount of money which is donated using raspberry pi. It can also be used in the number of places where there is an availability of large amount of coin and currency usage such as charities, banks and trusts. In this paper, we proposed to process the images of the input which is inserted into the hundi to find its denomination. The image processing is used to identify both the coins and currencies. Finally, the total amount is calculated by adding the monetary value of each image and displayed using LCD module. Thus, this system can reduce the human effort and also deduces the malpractice rate.

Arithmetic logic units and digital signal processors widely uses adders. It is the most complicated arithmetic circuits in digital electronics. The existing adders suffer from critical path delay, area overhead and power consumption. Speculative adders are designed with variable latency that combines speculation technique along with correction methodology to attain high performance in terms of low area overhead over the existing adders. In speculative adders the sum and carry generation part is separated to reduce the area overhead. Carry Speculative Adder (CSPA) uses carry predictor circuit to reduce power consumption and to reduce the computational time and it uses error recognition and error correction circuit to find the fault occurred in the partial sum generator and to recover it to get accurate results. This speculative adder can reduce the delay upto 11.88 %.

In recent engineering advances the convergence of internet, communication and information technologies will pave the way for new generation. Currently, distributed wireless sensor network plays significant responsibility in civilizing agricultural production and mitigating the agony of farmers. Soil moisture and temperature sensor are buried at the root zone of the plant. Owing to different climatic condition, Rain water sensor is located at the surface of the soil to deactivate the entire irrigation system during rainy season. The PIC microcontroller is used to gather the sensor information in real time. The data can be acquired and processed by sending and receiving the information from cultivation field. The measured data is allowed for data inspection with cellular internet interface to be graphically visualized through GPRS module. The whole irrigation system is powered by solar photovoltaic panel with battery power management system. The automated irrigation system is tested in turmeric and onion plantation simultaneously for 50 days. Water savings is up to 90% when compared with the present trickle irrigation channel is achieved. By incorporating the automated irrigation scheme, consumption of water and electricity is reduced, further it increases the quality of food grains and the yield of crops.

Runtime reconfiguration is a radical topic within the reconfigurable work out area, where fluctuations into the FPGA configuration are done at runtime, whereas the device input/output and lingering logic is kept active. This powerful feature only comprised in Xilinx and FPGAs permits not only to perform HW updates during runtime but also to reduce memory space and programming time compared to normal FPGA reconfiguration. This paper presents the design and implementation of an energy-aware sensor node, which can help in fabricating energy-efficient WSNs. An energy-efficient stratagem, which intentions at minimizing energy consumption from both the sensor node level and the network level in a WSN. According to WSN node the dynamic reconfiguration is scheduling under vitality garnering condition based on the statistical information on tasks and available energy. The experiments show that approach significantly reduces total power consumption up to 30% compared with previous works.

Reconfigurable techniques are used in many engineering and industrial applications for the efficient data transmissions through the wireless sensor networks. Nowadays, most of the industrial applications are working to try to minimize the size and cost. During runtime the reconfigurable technique avoids the unwanted hang and delay in the system performance. In recent world Field Programmable Gate Array (FPGA) as one of the most efficient reconfigurable devices and widely used for most of the hardware and software reconfiguration applications. In this paper, the work deals with whatever going to make changes in the hardware and software during runtime, it's should not affect the current running process that's the main objective of the paper our changes are done in a parallel manner at the same time concentrating the cost and power transmission problems during data transreceving. Analog sensor (Temperature) as an input for the controller (PIC) through that control the FPGA digital sensors in a generalized manner.

In real time process, multiple heterogeneous signals can be acquire with the help of data acquisition and processing (DAQP) and process them in real time process. The main objective of this technology is to monitor different levels of signals from different sensors without any additional usage of the hardware devices. The proposed system is design in system on chip via Field Programmable Gate Array (FPGA) to check the speed of the acquired signals. Various modules of the conceptual designs are implemented and verified using LabVIEW graphical programming. The hardware testing is implemented with the help of NI-DAQ and NI-FPGA. This testing allows for high speed processing and also keeping the device cost less.

The data acquisition and processing (DAQP) is design to acquire multiple heterogeneous signals and processing them in real time process. The main objective of this technology is to monitor different levels of signals from different sensors without any additional usage of the hardware devices. The proposed system is design in system on chip via Advanced RISC Machine (ARM) to check the speed of the acquired signals. Various modules of the conceptual designs are implemented and verified using Lab VIEW graphical programming. The hardware testing is implemented with the help of NI-DAQ and NI-ARM This testing allows for high speed processing and also keeping the device cost less.

The data acquisition and processing architecture covers the most demanding applications in continuous patient monitoring for chronic diseases in medical field. The multichannel data acquisition is essential for acquiring and monitoring the various biomedical signals from biomedical sensors or signals from industrial sensors. The problem is that the data storage and hardware size, so the multichannel data obtained is processed at runtime and stored in an external storage for future reference. The method of implementing the proposed design is the system on-chip via field programmable gate array (SoC-FPGA) to reduce the hardware size and for memory size. The Soc-FPGA attains high resolution and real time processing of data acquisition and signal processing. A four channel data acquisition and processing (DAQP) was designed, developed using the Lab VIEW graphical programming. NI DAQ and NI FPGA module is used to test and implement the design for real time. The module was designed inorder to provide high accuracy, storage and portability.

Intelligent data acquisition with real time data processing require an efficient algorithm to reduce the amount of redundant data collected during the acquisition process. Changing the sampling rate in accordance with acquired signal bandwidth will reduce the supererogatory information collected. In these case self-adaptive sampling rate is used that will continuously adapts the sample rate during the acquisition. Data are acquired continuously at fixed sample rate then the rest of the process is based on bandwidth estimation algorithm. Decimation factor for acquired signal was found out with the help of bandwidth estimation algorithm. The system optimizes the amount of data collected while retaining the same information.

Scratchpad Memories are widely employed in embedded systems as an alternative to caches because they achieve comparable performance with higher power efficiency. Here, Optimal SPM Mapping and Memory Power-Down techniques are used for minimize the total energy of the SPM. SPM mapping simply targets the minimum number of accesses to the main memory, i.e., active power. A global optimization should explicitly take into account memory access energy, leakage energy, and power-down/up energy penalty, to define the Optimal SPM mapping and Optimal memory power-down scheduling for minimizing the total energy in the memory sub-system. Synthesis results based on 1.32V CMOS standard-cell library shows that the proposed SPM reduces the power consumption by 25–30%.