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In a conventional current-mode dc–dc buck converter, two sensed inductor current signals are processed in three separate comparators to regulate the converter under various load conditions. These independent sensing currents and comparators not only consume large quiescent current and silicon areas but also cannot guarantee the accuracy of the current limit threshold. This article proposes a current-mode dc–dc buck converter with an accurate current limit using a multiplex pulsewidth modulation (PWM) comparator. Through a multiplex PWM comparator, only one sensing current and one comparator are required to process the inductor current information and complete the regulation of the converter under various load conditions. The response speed of overcurrent protection is also increased without consuming more power and silicon area. Moreover, by generating the zero temperature coefficient (ZTC) sensing current and adding ZTC reference current with slope compensation information, the accuracy of the current limit threshold is greatly improved under various temperatures in a wide input voltage range. The proposed buck converter with a multiplex PWM comparator was fabricated using a standard 1P3M 0.18 μm BCD (BiCMOS/DMOS) process and the experimental results show that the proposed scheme functions properly in the 5-A load range, and the current limit threshold also varies only 8.1% in the temperature range from −40 to 125 °C with the input voltage up to 60 V. [ABSTRACT FROM AUTHOR]

This article presents a one-stage buck converter with an accurate nanosecond ON-time ($T_{\mathrm{\scriptscriptstyle ON}}$) control for 48–1-V direct conversion for automotive applications. In order to overcome the low duty cycle from 48 to 1 V, the proposed high-voltage storage and low-voltage boost (HSLB) bootstrap circuit can reduce the level shifter delay to close to zero and the bootstrap delay to less than 2 ns. In addition, the early comparison $T_{\mathrm{\scriptscriptstyle ON}}$ generator can reduce the comparator delay ($T_{d\_{}{\mathrm{ comp}}}$) to close to zero at steady state to achieve precise nanosecond pulse $T_{\mathrm{\scriptscriptstyle ON}}$. On the other hand, $T_{d\_{}{\mathrm{ comp}}}$ can be quickly extended to increase $T_{\mathrm{\scriptscriptstyle ON}}$ by 540% to achieve fast transient with the recovery time of 3 $\mu \text{s}$ , in case load changes from 200 mA to 1 A. Based on the precise nanosecond $T_{\mathrm{\scriptscriptstyle ON}}$ , the OFF-time is extended by the load-dependent current limiting OFF-time modulation for improving light-load efficiency. Experimental results show that the peak efficiency reaches 96.5%, 95.1%, and 92.8% when $V_{\mathrm {IN}}$ is 12, 24, and 48 V, respectively, for $V_{\mathrm {OUT}} = 1$ V. [ABSTRACT FROM AUTHOR]

This article presents a fully passive noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) that can be compatible with dynamic voltage and frequency scaling (DVFS) schemes while offering a 12-bit resolution for Internet-of-Things (IoT) sensor applications. To realize a voltage-scalable suppression of the in-band quantization noise, the proposed ADC utilizes a second-order cascade of integrators with feedforward (CIFF) NS loop with a 3-input dynamic comparator, which can obtain an additional resolution of more than 3 bits. A cyclic dynamic element matching (CDEM) for MSB is seamlessly combined with the NS operation and simply realized by shift registers (SRs). The MSB CDEM reduces dominant in-band harmonic distortions due to capacitor mismatch by not only averaging out but also randomizing the MSB mismatch errors with modulation dither from the CIFF NS loop. In addition, a last-bit majority voting (LMV) technique is applied when resolving the LSB to reduce the comparator noise by half with four additional cycles. With both the LMV and CDEM techniques enabled, the SNR and SNDR are enhanced to 73.3 and 72.3 dB, respectively. The ADC achieves an ENOB of $11.2-11.7$ bits with a reconfigurable bandwidth of 10–50 kHz at a supply voltage of 0.6–1 V. The prototype ADC was fabricated using 28-nm CMOS technology, occupying an active area of 0.0575 mm2. [ABSTRACT FROM AUTHOR]

Low-activity signals, such as voice, electrocardiogram (ECG), and ultrasonic signals, in the Internet-of-Things applications have both posed unique challenges and offered special opportunities for modern analog-to-digital conversion. This article presents a new successive approximation register (SAR) analog-to-digital converter (ADC) search methodology, which is aimed at low-activity signals for reducing comparator activity and switching energy of digital-to-analog converter (DAC). By using statistical histogram information of the low-activity signals, two search solutions are proposed. The first solution is designed for some part of signal that has small difference between two adjacent samples, while the second solution is designed for that with large difference. To engage one suitable solution, the digital interval between two adjacent samples needs to be detected. In addition, a new DAC tactic is proposed to reduce the activity of DAC switches. Our simulated 10-bit SAR ADC for voice signals shows that by using our proposed method, the comparator activity is reduced by 62.09%, and the DAC switching energy is decreased by 85.90% compared to the monotonic method. In addition, the activity of DAC switches is further trimmed by 39.66% compared to the monotonic method. [ABSTRACT FROM AUTHOR]

This article proposes a scheme to design a broadband low-profile monopulse comparator for the dual-circularly polarized feeder. For obtaining a compact and easily integrated structure, a monopulse comparator with a ring-shaped symmetrical planner topology is proposed by using the 3 dB coupler and the phase shifter based on the groove gap waveguide (GGW). Then, in order to achieve the equal-amplitude distribution in a broad bandwidth, the asymmetrical coupling structure and the novel dispersion-matched transition are proposed to improve the directivity of a 3 dB coupler. Moreover, a ridge waveguide with periodic grooves featuring stable dispersion change is adopted to design the phase shifter, which contributes to obtain an accurate phase control in the broad frequency band. To validate experimentally the broadband performance, a dual-circularly polarized four-horn feeder with two identical monopulse comparators is designed and fabricated. The results show that the symmetrical radiation patterns with 32 dB null-depth can be obtained from 27 to 31 GHz. The monopulse comparator characterizes broad bandwidth, low loss, and a compact size, which provides a monopulse comparator with accurate amplitude/phase control for the research of the monopulse antenna. [ABSTRACT FROM AUTHOR]

This article presents a delta sigma modulator (DSM) analog to digital (ADC) that uses ring amplifiers as integrators to relax speed and efficiency bottlenecks in discrete-time (DT) oversampled ADCs. Its multi-bit quantizer is based on split source (SS) comparators, adding flexibility and power efficiency. The complete oversampling ADC is designed as a 3rd-order cascade of integrator with feed forward (CIFF) with a 4-bit quantizer, and it achieves a peak signal-to-noise and distortion ratio (SNDR) of 67 dB and DR of 70.0 dB with 47.5-MHz bandwidth when clocked at 950 MHz. This is the highest bandwidth reported to date among single-channel DT DSM ADCs and demonstrates a viable alternative to continuous-time (CT) DSM ADCs for wideband oversampling applications. With a power consumption of 4.7 mW from a 1-V supply, figure of merit (FoM) Schreier and Walden are 167.0 dB and 27.0 fJ/c.s, respectively, demonstrating efficient DT delta-sigma conversion with high bandwidth. [ABSTRACT FROM AUTHOR]

This article presents a 5-GS/s 6-bit flash analog-to-digital converter (ADC) in a 28-nm fully depleted silicon-on-insulator (FDSOI) CMOS process. The ADC jointly employs partially active second-stage comparison and $2\times $ time-domain latch interpolation (TDI) to reduce power consumption and avoid extensive calibrations. To enhance the conversion speed of the second-stage structure, the stringent timing constraint is resolved by a 25%–75% duty-cycle clock scheme, a 0.5-bit redundancy in the first comparison stage, and an embedded second-stage slice selection logic. The bandwidth requirements of the track-and-hold (T/H) and T/H buffer under the 25%–75% duty-cycle clock are analyzed. An on-chip successive-approximation (SA)-based comparator offset calibration scheme utilizing FDSOI back-gate bias is also developed, providing sufficient calibration range without impairing comparator speed. The measured prototype achieves a signal-to-noise and distortion ratio (SNDR) of 32.8 dB and a spurious-free dynamic range (SFDR) of 41.82 dB at Nyquist frequency while consuming 15.07 mW power, translating into a Walden figure-of-merit (FOM) of 84.5 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

This article presents a 0.975-pJ/bit 56-Gb/s pulse amplitude modulation-4 (PAM-4) receiver using a time-based least significant bit (LSB) decoder in 28-nm CMOS technology. The proposed time-domain decision technique improves the robustness of comparator voltage variations by separating the data and reference paths. If the reference voltage difference is constant regardless of the common-mode voltage shift, the time-domain decoder achieves a low bit error rate (BER). To improve the timing margin of the LSB decoder from the data-dependent jitter, a sample-and-hold (S/H) structure is adopted in both the data and reference paths. The S/H circuits extend the timing margin by converting the input of the comparators to a constant voltage. The number of comparators for data decoding is reduced to two-thirds, and only eight comparators are required for a quarter-rate structure. The number of comparators in the data path, excluding the reference path, is 4, which reduces the loading capacitance. An adaptive threshold voltage calibration was implemented to generate the timing reference pulse. In addition to bathtub graphs, the BER, according to the $V_{\text {CM}}$ change of the reference voltages, is plotted to show the sensitivity to the voltage variation. [ABSTRACT FROM AUTHOR]

A voltage-controlled oscillator (VCO)-based comparator that automatically adapts its noise performance reflecting the input voltage difference ($\Delta V_{\text {in}}$) is presented. Such adaptive operation significantly reduces the power of high-precision comparators in successive-approximation-register (SAR) ADCs. $\Delta V_{\text {in}}$ is integrated as a time difference via the VCO, where the integration continues as long as the time difference is below a certain threshold, defined by the phase detector deadzone. Thus, when $\Delta V_{\text {in}}$ is large, the comparator operates as a low-power delay line-based comparator, and with small $\Delta V_{\text {in}}$ , the VCO oscillates to integrate the input signal and suppresses the comparator noise. The required oscillations to complete the comparison are inversely proportional to $\Delta V_{\text {in}}$ , realizing fully adaptive noise and power scaling. This article provides a detailed analysis and specific design guidelines of the VCO comparator. Moreover, the PVT drift tolerance and detailed circuit implementations are deeply discussed as well. For proof-of-concept, a 13-bit SAR ADC with the proposed VCO-based comparator was fabricated in 65-nm CMOS. By off-chip LMS calibration, the ADC achieves peak SNDR 66 dB at 1 MS/s with a peak FoM of 29 fJ/conv.-step. [ABSTRACT FROM AUTHOR]

Today’s analog and mixed-signal (AMS) layout flow requires long manual iterations and does not leverage computing resources for data-driven optimization. This issue is further compounded by the explosion of design rules and layout-dependent effects (LDEs). We present an AMS layout generation flow that leverages digital place-and-route (PnR) tools, amortizes setup cost with reusable primitives, and prunes layout candidates using a fast evaluation scheme. We also analyze LDEs and parasitics and investigate unique challenges and mitigation strategies associated with using digital PnR tools for AMS circuits. These insights are validated with a generated StrongARM comparator and a voltage-controlled oscillator (VCO). The VCO layout was optimized in 2 h and fabricated in 16-nm FinFET CMOS. Silicon measurement results of the VCO closely track the simulation, verifying the methodology from netlist to silicon. [ABSTRACT FROM AUTHOR]

This article describes a 2.1-MHz relaxation oscillator (RxO) for energy-harvesting Internet-of-Things (IoT) sensor nodes. The RxO features an asymmetric swing-boosted RC network and a dual-path comparator to surmount the challenges of sub-0.5-V operation while achieving temperature resilience. The former enables alternating the common-mode voltages at the output of the RC network to facilitate the sub-0.5-V operation, while the latter is outfitted with a delay generator for tracking the temperature-sensitive delay of the comparator. Prototyped in 28-nm CMOS, the RxO occupies a tiny footprint of 5,200 μm2. The power consumption is 1.4 μW at 0.35 V. The measured temperature stability is 158 ppm/°C (average of seven chips) over −20 °C–120 °C. It scores the best energy efficiency (667 fJ/cycle) among the reported MHz-range RxOs and has a figure-of-merit (181 dB) that compares favorably with the state-of-the-art. [ABSTRACT FROM AUTHOR]

A $4\times $ interleaved pipelined ADC for direct-RF sampling applications is presented. It leverages the performance advantages of ring amplifiers to unlock greater architectural freedom. The first pipeline stage MDAC with a “passive-hold” mode eliminates the sub-ADC sampling path and associated problems. A high-speed ringamp topology employs digital bias control, robust common-mode feedback (CMFB), and an elegant self-resetting behavior. An asynchronous, event-driven timing control system improves several aspects of performance and enables fully dynamic power consumption and modular design re-use. A general technique is presented whereby the signal-to-distortion ratio (SDR) of any amplifier in the system can be measured in the background with an analog hardware overhead of only one comparator. In this amplifier-intensive architecture utilizing 36 ringamps, the 4-GS/s ADC fabricated in 16-nm CMOS achieves 62-dB SNDR and 75-dB SFDR at Nyquist, consumes 75 mW (including input buffer), and has a Walden figure of merit (FoM) of 18 fJ/conversion-step and a Schreier FoM of 166 dB, advancing the state of the art in direct-RF sampling ADCs by roughly an order of magnitude. [ABSTRACT FROM AUTHOR]

Analog-to-digital converters (ADCs) with different topologies respond differently to total ionizing dose (TID). A flexible behavioral modeling approach is proposed for system-level simulation of TID effects in successive-approximation-register (SAR) ADCs. The radiation-enabled approach can be adapted for a wide range of ADCs of various resolutions, clock speeds, and manufacturers. The empirical model is calibrated and validated, pre-rad and post-rad, for a particular ADC. Pre-rad calibration is performed by introducing distributions of static parameters corresponding to datasheet specifications. The post-rad calibration is accomplished by introducing error sources associated with the comparator and digital-to-analog converter (DAC), corresponding to experimental data. The calibrated model is used to examine the dynamic performance and to estimate the probability of parametric failure during the mission lifetime. [ABSTRACT FROM AUTHOR]

This brief presents a three-stage comparator and its modified version to improve the speed and reduce the kickback noise. Compared to the traditional two-stage comparators, the three-stage comparator in this work has an extra amplification stage, which enlarges the voltage gain and increases the speed. Unlike the traditional two-stage structure that uses pMOS input pair in the regeneration stage, the three-stage comparator makes it possible to use nMOS input pairs in both the regeneration stage and the amplification stage, further increasing the speed. Furthermore, in the proposed modified version of three-stage comparator, a CMOS input pair is adopted at the amplification stage. This greatly reduces the kickback noise by canceling out the nMOS kickback through the pMOS kickback. It also adds an extra signal path in the regeneration stage, which helps increase the speed further. For easy comparison, both the conventional two-stage and the proposed three-stage comparators are implemented in the same 130-nm CMOS process. Measured results show that the modified version of three-stage comparator improves the speed by 32%, and decreases the kickback noise by ten times. This improvement is not at the cost of increased input referred offset or noise. [ABSTRACT FROM AUTHOR]

This article demonstrates the integrated comparators, hysteresis comparators, and sawtooth generators based on aluminum–gallium–nitride/gallium–nitride (AlGaN/GaN) metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs). The integrated circuits (ICs) exhibit thermal stability from 25 °C to 250 °C in both static and transient performances. The threshold voltage (Vth) in depletion (D)-mode MIS-HEMT is modulated from −8.9 to −2.4 V to optimize the performance of integrated comparator circuits. The comparator can realize a large and stable comparison range of 3–9 V and a high voltage swing of 9.1 V, while the hysteresis comparator exhibits a good noise-immunity ability and stable hysteresis output. The sawtooth generator with the hysteresis comparator features a high amplitude (6.1 V) sawtooth signal at 500 kHz to realize a compact structure applicable to the high-voltage mixed-signal circuits. These results show the feasibility of MIS-HEMT monolithic comparator circuits in conversion systems. [ABSTRACT FROM AUTHOR]

The sensitivity of the LM139A quad voltage comparator toward simultaneous single-event transient has been investigated through laser single photon absorption. The results have been supported and compared to heavy-ion tests. The analysis of sensitivity leads to the observation of two sensitive cases related to internal charge-sharing mechanism between comparator function and input line coupling effects. [ABSTRACT FROM AUTHOR]

Non-destructive measurements of nA beam currents in particle beam storage rings by detecting the azimuthal magnetic field generated by moving charged particles with a Cryogenic Current Comparator (CCC) are well established. The detection of beam currents with small amplitudes with a CCC in a storage ring demands a high slew rate which is caused by the rapid change of the beam current exceeding the operational limit of the SQUID in flux-locked loop mode. Previous solutions to increase the slew rate used a LCR first-order low-pass filter were a small resistor, unfortunately, dominated the current noise of the CCC. In this work we present a novel take by adding a second resonator into the CCC which in turn allows for higher resistances of the LCR low-pass filter and therefore lower thermal current noise. A second challenge connected with this CCC approach is the residual magnetization of the highly permeable magnetic core and the resulting shielding currents in the superconducting circuits of the CCC. The timing of a storage ring in the range of minutes opens a way to reduce these DC currents using a LR high-pass filter. Using serial sub-micro ohm resistors, time constants in the hour range can be achieved to improve the stability and performance of the CCC system. [ABSTRACT FROM AUTHOR]

Silicon physical unclonable function (PUF) has emerged as a promising spoof-proof solution for low-cost device authentication. Due to practical constraints in preventing phishing through a public network or insecure communication channels, simple PUF-based authentication protocol with unrestricted queries and transparent responses is vulnerable to modeling and replay attacks. In this article, we present a modeling attack resistant PUF-based mutual authentication scheme to mitigate the practical limitations in applications where a resource-rich server authenticates a device with no strong restriction imposed on the type of PUF design or any additional protection on the binary channel used for the authentication. Our scheme uses an active deception protocol to prevent machine learning (ML) attacks on a device with a monolithic integration of a genuine strong PUF (SPUF), a fake PUF, a pseudorandom number generator (PRNG), a register, a binary counter, a comparator, and a simple controller. The hardware encapsulation makes the collection of challenge–response pairs (CRPs) easy for model building during enrollment but prohibitively time consuming upon device deployment through the same interface. A genuine server can perform a mutual authentication with the device using a combined fresh challenge contributed by both the server and the device. The message exchanged in clear cannot be manipulated by the adversary to derive unused authentic CRPs. The adversary will have to either wait for an impractically long time to collect enough real CRPs by directly querying the device or the ML model derived from the collected CRPs will be poisoned. The false PUF multiplexing is fortified against the prediction of waiting time by doubling the time penalty for every unsuccessful guess. Our implementation results on field-programmable gate array (FPGA) device and security analysis have corroborated the low hardware overheads and attack resistance of the proposed deception protocol. [ABSTRACT FROM AUTHOR]

A monopulse horn feed with a triple-radiation pattern (sum, elevation difference, and azimuthal difference) operating at 35 GHz is presented. The device consists of three main parts: a spline profiled horn, a mode converter that generates the modal field combinations that produce each radiation pattern, and a very compact single-layer monopulse comparator network. Unlike other state-of-the-art designs, the novel feed is based on a triple-radiation pattern horn with a mode converter excited by a comparator network implemented in a single level for improving the compactness and easing quasi-2-D manufacturing. The kernel of this network is a novel 180° H-plane waveguide coupler with in-line ports, which avoids any additional phase compensation in the routing waveguide sections used in other works. The design process of the Ka-band antenna feed is described, and the simulated results for the three radiation patterns and their associated reflection coefficients are presented. The prototyping process is outlined, and the obtained experimental results are compared with the simulated ones showing very good agreement and validating the design process. [ABSTRACT FROM AUTHOR]

On-chip oscillators are popular clocking solutions for a wide range of circuits and systems due to their ease of integration and low form factor, but their energy efficiency is typically limited to the pJ/cycle range by a number of contributors, such as active biasing currents, frequency dividers, and comparators. This work presents an on-chip oscillator for energy-efficient Internet-of-Things (IoT) applications based on a duty-cycled digital frequency-locked loop (DFLL) that reduces energy by disabling energy-hungry components and only periodically reactivating them to keep the output frequency stabilized during temperature drifts. A test chip is implemented in 65-nm CMOS and achieves 18.8 fJ/cycle (10.5 nW at 560 kHz) while maintaining an average steady-state temperature stability of 96.1 ppm/°C from 0 °C to 100 °C. [ABSTRACT FROM AUTHOR]

Unlike transitional semiconductors, graphene has zero bandgap and symmetric electron/hole transport, which leads to unique V-shaped transfer characteristics. Using this property, we design and demonstrate a new type of comparator, which can calculate the absolute distance between two signals, |A-B|, directly. Dual-gate graphene transistors with ferroelectric hafnium zirconium oxide are fabricated to serve as the basic units of the comparators. We show that the remanent polarization of the ferroelectric hafnium oxide can reach ~ 30 μC/cm2 and the output current of the comparator can serve as a scalar indicator of the similarity level between two signals. The embedded ferroelectric layer can store the reference signal in situ, which will reduce the energy consumption and latency related to the data transport. Furthermore, we demonstrate the feasibility of using ferroelectric graphene comparator in image classification and motion detection. Using the k-nearest neighbors (KNNs) algorithm, we show that the graphene comparator arrays can recognize the handwritten digits in the modified national institute of standards and technology (MNIST) data set with over 80% accuracy. These ferroelectric graphene comparators will have broad applications in robotics, security system, self-driving vehicles, and sensor networks. [ABSTRACT FROM AUTHOR]

This article presents an enhanced interstage gain error shaping (GES) technique that adopts a digital error feedback (DEF) method to address the truncation error in the prior implementation, which can extend the interstage gain error tolerance by five times. The proposed DEF technique does not introduce additional errors as it operates purely in the digital domain. This article also proposes a first-order passive quantization noise shaping (NS) technique that reduces the input-pair ratio of the two-input-pair comparator by 2.7 times, thus alleviating the noise penalty caused by using a multiple-input-pair comparator. A prototype analog-to-digital converter (ADC) equipped with the proposed techniques in a 40-nm CMOS technology achieves a 77.1-dB signal-to-noise-and-distortion ratio (SNDR) over 6.25-MHz bandwidth while operating at 100 MS/s and consuming 1.38 mW. It achieves a 173.7-dB Schreier figure of merit (FoM). [ABSTRACT FROM AUTHOR]

In this article, a long-range length comparator, applicable for both static- and dynamic-index calibrations of a linear displacement sensor, is presented. The comparator consists of an air-floating linear motion generator (LMG) and an interferometric optical length calibrator (OLC). A novel design of the LMG made by multisegment splicing is introduced, in which a two-level vibration isolation arrangement, a multiple sliders’ setup, and an exoskeleton framework are adopted. The resulting linear motion can be extremely ideal even with a large stroke. The angular error is within $11.89~\mu $ rad covering the 12-m range. The maximum operating speed and the acceleration of the LMG are 10 m/s and 20 m/s2, respectively. A dual-path optical design of the OLC is displayed, resulting in high environmental tolerance and a small trigger delay of 4.75 ns. The best accuracy of the comparator can be ±($0.041+ 0.106L) \mu \text{m}$ with a resolution of 0.3 nm. The maximum error and operation speed of a 2-m range exposed encoder were successfully calibrated, and the grating pitch deviation was also found, by which the effectiveness of the comparator is proven. The proposed length comparator introduces a possible solution, for how a long-range linear displacement sensor, can be calibrated with high accuracy, efficiency, and applicability. [ABSTRACT FROM AUTHOR]

A new resistance bridge has been built at the Laboratoire national de métrologie et d’essais (LNE) to improve the ohm realization in the Système International (SI) of units from the quantum Hall effect. We describe the instrument, the performance of which relies on two synchronized and noise-filtered current sources, an accurate and stable current divider, and a cryogenic current comparator (CCC) having a low noise of $\mathrm {80~pA.t/Hz^{1/2}}$. The uncertainty budget for the measurement of the 100- $\Omega /(R_{\textrm {K}}/2)$ resistance ratio, where $R_{\textrm {K}}$ is the von Klitzing constant, amounts to a few parts in $10^{10}$ only. [ABSTRACT FROM AUTHOR]

This brief presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with two passive integrators. Due to the separation of the preamplifier, these two integrators become independent of each other and the size of the second integrator can be reduced. The NS SAR also realizes the zeros optimization of the noise transfer function (NTF). The analysis shows the NS performance of the proposed ADC is insensitive to the gain variation of the multipath comparator. To mitigate the harmonic distortion caused by capacitor mismatch, thermometer-code 4-bit MSBs are implemented with data weighted averaging (DWA) technique. The overall architecture is simple and robust, which only requires minor modifications to the standard SAR ADC. A prototype 9-bit NS-SAR ADC is designed and simulated in a 130-nm CMOS process. It consumes $59.9~\mu \text{W}$ of power when operating at 2-MS/s sampling frequency. The proposed ADC achieves peak Schreier figure of merits (FoMs) of 171.9 dB with 78.69-dB signal-to-noise-and-distortion ratio (SNDR) at an oversampling ratio (OSR) of 8. [ABSTRACT FROM AUTHOR]

A novel voltage comparator, termed an edge-race comparator (ERC), is proposed in this article. It compares the differential input voltage by generating two propagating edges in two inverter loops and by measuring the distance between the two edges. The two edges race with each other and the winner is finally determined. The comparator is low power and low noise and does not require high-voltage headroom. It can automatically adjust its noise, power consumption, and delay according to the input voltage, thereby saving significant energy and time in coarse comparisons and reducing the noise in fine comparisons (noise averaging is performed over a longer time in fine comparisons). It is well suited for low-power, high-resolution successive approximation register (SAR) analog-to-digital converters (ADCs) (SAR ADCs). Compared to a recently published edge-pursuit comparator (EPC), the proposed structure achieves 3.39 times faster speed at 1-mV input by using a novel configuration of two inverter loops with a distance measurement circuit. The energy consumption per comparison is reduced by 2.73 times at 1-mV input owing to the shorter required comparison time. Designed in a standard 40-nm CMOS process, the measurement results from an ADC show that the comparator energy at the LSB is reduced by 7.5 times, and the ADC sampling rate is increased by 3.85 times. [ABSTRACT FROM AUTHOR]

Buffering architectures and policies for their efficient management are core ingredients of a network architecture. However, despite strong incentives to experiment with and deploy new policies, opportunities for changing anything beyond minor elements are limited. We introduce a new specification language, OpenQueue, that allows to express virtual buffering architectures and management policies representing a wide variety of economic models. OpenQueue allows users to specify entire buffering architectures and policies conveniently through several comparators and simple functions. We show examples of buffer management policies in OpenQueue and empirically demonstrate its impact on performance in various settings. [ABSTRACT FROM AUTHOR]

This article reports a power-efficient $8\times $ time-interleaved (TI) 2.4-GS/s 10-bit successive-approximation-register (SAR) analog-to-digital converter (ADC). To optimize the circuit design in terms of power efficiency and conversion rate, several enhancement techniques are presented. First, a pre-defined bypass window, introduced by the customized non-binary DAC, is used to modestly reduce the power consumption. Several conversion cycles are skipped as the input signal falls within the bypass window. Second, to enhance the operation speed, two alternate comparators are adopted in each ADC channel, and an opportunistic adaptive comparator offset calibration is proposed to eliminate the conversion rate degradation caused by the dedicated calibration cycle. The comparator offset is calibrated only when the bit bypass is triggered with the calibration step size adaptively set to acquire both fast convergence and small algorithm noise. In addition, the reference voltage of each ADC channel is provided by a pre-charged reservoir to avoid inter-channel crosstalk without the introduction of power-hungry-distributed reference buffers. A test chip is fabricated in a 28-nm fully depleted silicon on insulator (FDSOI) process with a core area of 0.11 mm2, including the reference charge reservoirs. Clocked at 2.4 GS/s, the proposed ADC measures a 49.02-dB signal-to-noise-and-distortion ratio (SNDR) at Nyquist while consuming only 9.8 mW from a 0.9-V supply, thus resulting in Walden and Schreier figures of merit (FOMs) of 17.7 fJ/conversion-step and 159.9 dB, respectively. [ABSTRACT FROM AUTHOR]

In this brief, a 300-mV, auto shutdown comparator based on a novel clock gating network is proposed. The proposed auto shutdown comparator is further employed to realize a compact, ultralow power continuous-time $\Delta \Sigma $ modulator (CTDSM) with a 300-mV supply voltage for multichannel sensing and biomedical applications. The design was fabricated in standard mixed-mode 180-nm CMOS process. Measurement results show that the CTDSM achieves a peak SNDR of 54.81 dB and DR of 57.4 dB while consuming a core power of $1.76~\mu \text{W}$ at 300-mV supply voltage without the clock-gated comparator. With the clock-gated auto shutdown comparator, the CTDSM consumes a core power of only 220 nW thereby providing an eight times power saving. Moreover, the fabricated CTDSM occupies an extremely small area of 0.0464 mm2 with an energy efficiency of 24.5 fJ/conv making it the most compact and energy-efficient CTDSM reported till date among the moderate resolution CTDSMs. Furthermore, by increasing the supply voltage to 400 mV, the CTDSM features a peak SNDR of 58.56 dB and DR of 64.1 dB while consuming a core power of 410 nW and 29.61 fJ/conv. [ABSTRACT FROM AUTHOR]

In this article, a compact physical unclonable function (PUF) based on cross-coupled comparator is presented. Featuring a positive feedback response generation mechanism, the mismatch in analog signals between the cross-coupled transistor pair is quickly amplified to prevent its polarity from flipping by the temporal noise. The rapid enlargement of noise margin by the sense amplifier also contributes to stabilizing the response against supply voltage variations. To improve its temperature stability, the counteracting effect of complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) drives are considered in sizing the bit cell transistors. The proposed design is fabricated in a standard 65-nm CMOS process. The bit cell occupies an area of only $4.38~\mu \text {m}^{2}$ (i.e., $1036~F^{2}$), and the overall PUF chip consumes 2.98 pJ/bit at the throughput of 8 Mb/s, of which only 1.61 pJ/bit is due to the PUF’s core. With the uniqueness measured to be 49.53%, the unpredictability of the fabricated PUF chips is validated by autocorrelation function and NIST randomness tests. Compared with the state-of-the-art implementations, the proposed PUF has the lowest native response instability of 1.46% with 500 repeated PUF readouts at 27 °C and 1.2 V. By varying the operating temperature from −50 °C to 150 °C in a step size of 10 °C and the supply voltage from 1.0 to 1.4 V in a step size of 0.1 V simultaneously, the average reliability of the proposed PUF obtained from the 2-D plot of all operating conditions is found to be 96.87% without correction and 99.31% with spatial majority voting (SMV). [ABSTRACT FROM AUTHOR]

The dual-coupled-linear congruential generator (LCG) (dual-CLCG) is a secure pseudorandom bit gene-rator (PRBG) method among various linear feedback shift register (LFSR), LCG, and chaotic-based PRBG methods for generating a pseudorandom bit sequence. The hardware implementation of this method has a bottleneck due to the involvement of inequality equations. Initially, a direct architectural mapping of the dual-CLCG method is performed. Since two inequality equations are involved for coupling, it generates pseudorandom bit at unequal interval of time that leads to large variation in output latency. In addition, it consumes a large area and fails to achieve the maximal period. Hence, to overcome the aforesaid drawbacks, a new efficient PRBG method, i.e., “coupled-variable input LCG (CVLCG),” and its architecture are proposed. The novelty of the proposed method is the coupling of two newly formed variable input LCGs that generates pseudorandom bit at every uniform clock rate, attains maximum length sequence, and reduces one comparator area as compared to the dual-CLCG architecture. The proposed architecture is implemented using Verilog-HDL and prototyped on the commercially available field-programmable gate array (FPGA) device. Furthermore, the sequences are captured through the logic analyzer and evaluated for randomness using the National Institute of Standard and Technology (NIST) standard test tool. The experimental result reports that the proposed PRBG method passes all the randomness tests with a high degree of consistency. [ABSTRACT FROM AUTHOR]

A microwave device able to detect differential-mode to common-mode conversion (or vice versa) in a four-port balanced circuit is proposed. For mode conversion detection, the balanced circuit should be fed by a differential-mode signal, generated by means of a rat-race balun from a single-ended signal. By connecting the pair of output ports of the balanced circuit under test to one of the two pairs of isolated ports of a second rat-race coupler, conversion to the common-mode (if it exists) can be detected and recorded in the $\Sigma $ -port. Since the signal level at the output (single-ended) port depends on mode conversion efficiency, the complete two-port structure, including the pair of rat-race couplers plus the balanced circuit in between, can be used as a comparator or differential microwave sensor based on mode conversion. In such a sensor, the working principle is symmetry disruption (caused, e.g., by an asymmetric dielectric load), and the output variable is the transmission coefficient, related to the level of asymmetry. A detailed analysis, considering an arbitrary unbalanced four-port test structure (to account for symmetry disruption), is carried out. Then, such analysis is particularized to the case of a pair of unbalanced and uncoupled matched lines, and the conditions for sensitivity optimization are obtained. Finally, a differential sensor and comparator based on a pair of balanced (and meandered) matched lines, designed according to the guidelines for sensitivity optimization, is fabricated and validated. [ABSTRACT FROM AUTHOR]

This article presents an energy-efficient comparator design. The pre-amplifier adopts an inverter-based input pair powered by a floating reservoir capacitor; it realizes both current reuse and dynamic bias, thereby significantly boosting $g_{m}/I_{D}$ and reducing noise. Moreover, it greatly reduces the influence of the process corner and the input common-mode voltage on the comparator performance, including noise, offset, and delay. A prototype comparator in 180 nm achieves 46- $\mu \text{V}$ input-referred noise while consuming only 1 pJ per comparison under a 1.2-V supply. This represents greater than seven-time energy efficiency boost compared with a strong-arm (SA) latch. It achieves the highest reported comparator energy efficiency to the best of our knowledge. [ABSTRACT FROM AUTHOR]

This brief presents a background calibration technique for pipelined successive-approximation-register (pipelined SAR) analog-to-digital converters (ADCs), which resolves the errors from capacitor mismatches and inaccurate interstage gain errors. The dither signal is injected in the capacitor digital-to-analog converter (DAC), while its residue voltage increment is neutralized through paired comparators with opposite polarity offsets, thereby relaxing the design requirement of the residue amplifier. While one of the comparators is generating the residue signal, the other one is detecting the signal range and helping to obtain the bit weights. This brief also introduces the circuit design of paired comparators with opposite offsets. The background calibration technique is verified in a 5b + 8b pipelined SAR ADC. Simulation results show that the spurious-free dynamic range (SFDR) and the signal-to-noise and distortion ratio (SNDR) are improved from 54.5 to 94 dB and 49 to 68.9 dB, respectively. The mean value of the voltage swing increment is 34 mV with noise sources, offset, gain error, and capacitor mismatches. [ABSTRACT FROM AUTHOR]

This paper presents an evolutionary developmental method for the design of arbitrarily growing sorting networks. The developmental model is based on a parallel rewriting system (a grammar) that is specified by an alphabet, an initial string (an axiom), and a set of rewriting rules. The rewriting process iteratively expands the axiom in order to develop more complex strings during a series of development steps (i.e., derivations in the grammar). A mapping function is introduced that allows for converting the strings onto comparator structures—building blocks of sorting networks. The construction of the networks is performed in such a way that a given (initial) sorting network grows progressively by adding further building blocks within each development step. For a given (fixed) alphabet, the axiom together with the rewriting rules themselves are the subjects of the evolutionary search. It will be shown that suitable grammars can be evolved for the construction of arbitrarily large sorting networks that grow with various given sizes of development steps. Moreover, the resulting networks exhibit significantly better properties (the number of comparators and delay) in comparison with those obtained by means of similar existing methods. [ABSTRACT FROM AUTHOR]

In-memory computing based on multivalued memristive device opens the vision of building computing system with less resource and high performance. In this article, we achieved three distinguishable resistance states in mature one-transistor-one-resistor (1T1R) memristor. Furthermore, based on a single multivalued 1T1R device, for the first time, we successfully demonstrated an area-efficient in-memory digital comparator, which will cost five logic gates in complementary metal oxide semiconductor (CMOS) approach. The method is also easily expanded to multibit. Our work could be a representative of using multivalued nonvolatile memory device in digital information processing with improved performance. [ABSTRACT FROM AUTHOR]

In this article, we propose a method for designing online totally self-checking (TSC) comparators for TSC systems implementable on field-programmable gate arrays (FPGAs). This method can be used to conduct exhaustive online diagnostics of each lookup table (LUT), which involves mapping the fundamental components of the comparator, with a small number of test patterns by directly measuring output of each LUT. Our method drastically reduces the number of test patterns for exhaustive diagnosis on the order of the input number n [ $O(n)$ ] (n is the input number to the comparator) while maintaining 100% coverage, even if we only know the specifications of the LUT without knowing its detailed structure. FPGAs will be easily applicable to systems that require high dependability. To confirm the soft error rate (SER) in a static random-access memory (SRAM)-based FPGA, we also conducted an experiment involving a single-event upset (SEU) caused by neutron radiation. For this experiment, we designed an FPGA implementation of 1575 identical dual-modular-redundant TSC comparators. The experiment was conducted for 10.4 h, and 34 errors were observed regarding such failures in comparator function. The evaluated SER for the TSC comparator with the proposed method was 0.055 FIT at sea level of New York City. [ABSTRACT FROM AUTHOR]

Gallium nitride (GaN) high electron mobility transistors (HEMTs) are promising power devices due to their excellent characteristics. However, GaN HEMTs have vulnerable gates that are susceptible to noise and voltage spikes, limiting their implementation in power converters. This paper presents a GaN HEMTs half-bridge driver with bandgap reference comparator clamping (BGRCC) and dual level shifters (DLS) for high switching frequency automotive applications. The BGRCC scheme can adaptively clamp the bootstrap rail voltage at an appropriate level with acceptable voltage ripples, which guarantees the safety of high-side GaN HEMT. Meanwhile, DLS scheme is applied in both the high- and low-side driving path to effectively drive the GaN HEMTs with low propagation delay and high dv/dt immunity. The proposed driver is fabricated in 0.18 μm high voltage bipolar-complementary metaloxide semiconductor (CMOS)-double-diffused metaloxide semiconductor (DMOS) process and can support 2–10 MHz operating. The functionality and performance are verified by experimental results. A buck converter utilizing this driver with GaN HEMTs can achieve maximum efficiency of 91.58% with quite electromagnetic interference behavior in the 16.5-W output power rating when operating at 2 MHz, which is superior to conventional silicon-based power converters and suitable for automotive applications. [ABSTRACT FROM AUTHOR]

For the first time, a leaky integrate-and-fire (LIF) neuron with both excitatory and inhibitory characteristics is demonstrated using a single MOSFET. No additional circuits such as comparator, reset circuit, or current-to-voltage converter as well as a membrane capacitor are needed, and thus the LIF neuron is realized with a footprint of 6 F2. Because of its gate terminal, neuron firing is selectively inhibited, which can improve the energy efficiency of the neuromorphic system by inducing sparse activity. Furthermore, the spiking property of the neuron can be controlled by the gate, which can provide additional room to enhance the classification accuracy. [ABSTRACT FROM AUTHOR]

This article presents a cascaded architecture of a frequency synthesizer to generate ultra-low-jitter output signals in a millimeter-wave (mmW) frequency band from 28 to 31 GHz. The mmW-band injection-locked frequency multiplier (ILFM) placed at the second stage has a wide bandwidth so that the performance of the jitter of this frequency synthesizer is determined by the GHz-band, digital subsampling phase-locked loop (SSPLL) at the first stage. To suppress the quantization noise of the digital SSPLL while using a small amount of power, the optimally spaced voltage comparators (OSVCs) are presented as a voltage quantizer. This article was designed and fabricated using 65-nm CMOS technology. In measurements, this prototype frequency synthesizer generated output signals in the range of 28–31 GHz, with an rms jitter of less than 80 fs and an integrated phase noise (IPN) of less than −40 dBc. The active silicon area was 0.32 mm2, and the total power consumption was 41.8 mW. [ABSTRACT FROM AUTHOR]

Negative-capacitance FETs (NCFETs) are a promising candidate for low-power circuits with intrinsic features, e.g., the steep switching slope. Prior works have shown potential for enabling low-power digital logic and memory design with NCFETs. Yet, it is still not quite clear how to harness these new features of NCFETs for analog functionalities. This article provides more insights into the circuit design space with new device characteristics and investigates its deployment in analog circuits, specifically, time-domain analog-to-digital converters (ADCs) and phase-locked loops (PLLs). We propose and optimize a novel digital-based clocked comparator and a capacitor-based voltage-to-time converter (VTC), which are essential building blocks in ADCs and PLLs. Evaluation results show beyond-FinFET comparison speed and enhanced linearity for the proposed NCFET-based clocked comparator and VTC, respectively. Such improvement is achieved by exploiting the steeper slope and increased output impedance of NCFETs. More details on design details and a discussion are provided in this article. [ABSTRACT FROM AUTHOR]

A current-mode hysteretic buck converter is described in which inductor current is sensed by a resistor-capacitor (RC) network. The inductor current sensing RC network is reset multiple times per switching clock period, which allows it to have time constant much smaller than switching clock period and therefore occupy small silicon area. A frequency regulator ensures the switching frequency to be constant regardless of the operating condition of the buck converter and also integrates comparator delay compensator as its loop filter. The current-mode hysteretic buck converter implemented in a 65 nm complementary metal-oxide-semiconductor (CMOS) process provides 0.6–2.0 V output from 3.3 V input with 1 MHz switching frequency. The maximum load current is 1.5 A and the measured peak power efficiency is 96.3%. [ABSTRACT FROM AUTHOR]

This article proposes a power-efficient highly linear capacitor-array-based digital-to-time converter (DTC) using a charge redistribution constant-slope approach. A fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate the starting supply voltage of the constant discharging slope fed to a fixed-threshold comparator. The DTC operation mechanism is analyzed and design tradeoffs are investigated. The proposed DTC consumes merely 31 $\mu \text{W}$ from a 1-V supply when clocked at 40 MHz, while achieving a fine resolution of 148 fs over a 9-bit range. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.96/1.07 LSB. [ABSTRACT FROM AUTHOR]

Realizing the vision of a trillion IoT sensor nodes demands ultra low-power (ULP) compute, typically implemented using synchronous digital systems. These require low-power clock sources which must be fully integrated to meet low system-cost requirements. Hence, relaxation oscillators (RxOs) are popular. Their need for precision references and high-speed comparators can challenge power budgets; hence, prior works have explored low-speed closed-loop control for RxOs to alleviate this issue. This paper adopts an alternative approach to minimize the RxO power: the use of a ratioed switched-capacitor reference and sub-clock power-gating of the high-power comparator. The stability of the proposed design is further enhanced through the integration of digital-assist. This mixed-signal approach allowed a 1.2-MHz RxO to be implemented in 0.005 mm2 in TSMC 65 nm, with silicon measurements showing 0.7%/V line and 100 ppm/°C temperature stability. The energy-per-cycle figure of merit is 0.68 nW/kHz—a 4 $\times $ improvement over state-of-the-art for comparable stability. [ABSTRACT FROM AUTHOR]

In this paper, a resolution enhancement method for direct interfacing of inductive sensors, without employing analog-to-digital converter and/or external driver circuit, is presented. In order to achieve better resolution with minimum relative error and current consumption factors, different schemes are implemented which vary in terms of: 1) step-input voltage provision methodology, i.e., through microcontroller ($\mu \text{C}$) pin or through external supply; 2) number of switches used; and 3) method of voltage detection, i.e., either using capture module or employing built-in comparator only. The maximum achievable resolution limits are explored by reducing the lower reference voltage ($\text{V}_{\mathrm {Ref L}}$) in case of detection through built-in analog comparator and/or reducing the series resistance. The one-point calibration technique is used to determine the accuracy. The experiments are performed at 16-MHz clock frequency in the inductance range of: 1) 10–100 $\mu \text{H}$ and 2) 100–1000 $\mu \text{H}$. The results show that in the limits of a maximum current sourcing/sinking capacity of a typical $\mu \text{C}$ , i.e., 40 mA, the proposed methodology enhances the resolution to $4~\mu \text{H}$ with a relative error of 1.2 in the percentage of full-scale span (%FSS). The maximum nonlinearity error in %FSS for inductance range 10–100 $\mu \text{H}$ and 100–1000 $\mu \text{H}$ is 1.1% and <0.4%, respectively. [ABSTRACT FROM AUTHOR]