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The asymmetric conductance modulation of resistance random access memory (RRAM) is one of the crucial obstacles of the application as artificial synapses for online training. In this work, an optimized programming scheme is proposed to overcome the obstacle. In the optimized programming scheme, the RRAM is grounded through the array parasitic capacitor during the depression process. By harnessing the charging effect of parasitic capacitor, the voltage applied on the RRAM-based synapse is self-regulated according to its conductance. Meanwhile, the linearity of depression process can be tuned by adjusting the operation pulse shape to realize symmetric conductance modulation. The proposed programming scheme is verified by experiment and simulation with a 4 kb RRAM array. Finally, the optimized programming characteristics are applied in the simulation of the training of a VGG-like neural network for the classification of CIFAR-10 dataset. The results show that with the linearity of 6, 88.93% training accuracy is achieved, showing 17.3% accuracy improvement without any overhead either in fabrication process or hardware design cost. [ABSTRACT FROM AUTHOR]

Electromigration (EM) of metal interconnects is the continuous reliability concern for high-density integration beyond 5-nm technology, especially for the buried power rails in vertically stacked device structure. In this work, EM reliability of alternative metal interconnects based on complementary FET (CFET) is investigated by kinetic Monte Carlo (KMC) method. The microscopic evolutions of void formation in power rails can be well reproduced by considering the coupled effects of thermal and stress distribution during the EM simulation. The influences of grain boundary in different metal materials on EM lifetime are analyzed to provide the optimal strategy of process integration. Thermal-aware EM reliability is further predicted, indicating the importance of self-heating on EM evaluation of power rails in CFET. [ABSTRACT FROM AUTHOR]

In this article, we investigate the self-heating effect (SHE) of the Complementary FET (CFET) device and propose a cross-coupled thermal network model. For the investigation of thermal behavior, the intra- and inter-device crosstalk of CFET is evaluated qualitatively through the defined crosstalk coefficient. The results indicate that CFETs have more severe intra-device thermal crosstalk, almost twice that of CMOS. Moreover, the vertical structure makes the heat dissipation path of CFET devices significantly different in the two transition states (inputs “1” and “0”). Based on the thermal behavior characteristics of CFET and the necessity of high-precision and rapid prediction of thermal characteristics of the devices, a thermal network model is proposed, which can quickly respond to the heat source and be extended at the array level. In the last part, we analyze the influence of load capacitance and operating frequency on the self-heating of CFET, and SHE-related reliability lifetime is predicted based on the lattice temperature obtained from the thermal network. The prediction results show that the bias temperature instability (BTI) lifetime of CFET degrades by 84% compared with standard CMOS. [ABSTRACT FROM AUTHOR]

In this letter, a new method based on the temperature dependence of gate leakage current for accurately characterizing thermal crosstalk is proposed and performed on the advanced silicon-on-insulator (SOI) MOSFETs. The developed technique enables to capture the pure thermal crosstalk effect as it excludes the self-heating impact during the measurement. Moreover, it is proven robust over a large range of gate voltages regardless of the difference of device types, which is demonstrated on a pair of devices with a shared port. The accuracy of the thermal crosstalk measurement benefits in determining the overall thermal performance of the nano-scaled circuits under the mutual heating impacts. It offers a possible hardware solution to thermal monitor and management. [ABSTRACT FROM AUTHOR]

Independent back bias in the ultrathin body and Box (UTBB) fully depleted silicon-on-insulator (FDSOI) serves as the critical knob for exploiting the performance and power tradeoffs and process/aging compensation. The effectiveness of back bias is one of the major metrics in the stages of circuit design and runtime feedback. In this article, new closed-form expressions accounting for the interface traps and short channel effects-dependent back gate capability in the UTBB FDSOI device are proposed. The developed model allows the accurate assessment of body factor (γ) with the dependence of front/back interface trap density in the ultrascaled FDSOI device, taking the impact of gate area scaling as well as quantum effects into account. It also facilitates the evaluation of back bias effectiveness variability induced by interface traps and benefits the dynamic threshold voltage strategy in terms of adaptive back-biasing for performance optimization, which is consistent with 3-D device simulations and measurements. Moreover, the results confirm that γ variability follows Pelgrom’s rule. [ABSTRACT FROM AUTHOR]

A new method using temperature dependent shared series resistance in a pair of devices with common drain configuration is proposed to measure self-heating (SH) in advanced MOSFETs. The proposed measurement technique depends on the intrinsic series resistance and is not limited to the spatial proximity between the heater and the sensor. The developed method demonstrated on the silicon-on-insulator (SOI) MOSFETs reveals that the more accurate SH assessment can be obtained compared to other methods that are sensitive to the distance from heat source. Furthermore, the extraction of intrinsic series resistance allows to quantify the process-induced variability of the contact resistance. [ABSTRACT FROM AUTHOR]

Many efforts have been reported to improve the linear conductance modulation of analog RRAM for neuromorphic computing, while the related model for analog switching is still lacking. In this letter, we propose a physics-based analytic model to account for analog behavior of HfO2-based RRAM. The switching from abrupt SET process to gradual SET is analyzed quantitatively by considering the electrical and thermal effects of intermediate modulation layer (IML). The proposed model well describes the conductance update in potentiation and depression, which is validated with the experimental data. The results show that for the case of introducing IML to improve linearity, the electrical resistivity of IML has a greater effect than thermal conductivity on the control of oxygen vacancy generation rate, thus playing a dominant role in the nonlinearity optimization of analog RRAM. [ABSTRACT FROM AUTHOR]

As a promising new generation of nonvolatile memory, HfO2-based resistive random-access memory (RRAM) has attracted extensive research. However, the problem of data retention has prevented its industrial production as embedded memory. In this paper, from the microscopic understanding, a Monte Carlo simulator is developed to investigate the effects of an oxygen reservoir layer (ORL) on the resistance instability of HfO2-based RRAM. The evolution of conductive filaments (CF) during the retention degradation is visualized by our simulation considering the physical mechanisms of oxygen ions absorbed and released by the ORL. The simulation results are further validated with experiments to provide the prediction of retention performance of RRAMs with different ORLs and operation schemes. [ABSTRACT FROM AUTHOR]

Aggressively scaled devices with high power density wrapped around the low thermal conductivity material in narrow space are susceptible to self-heating effect, which includes serious mutual-heating due to proximity effect in multifinger/fin FETs. Obtaining local temperature instead of equivalent lumped temperature at device/circuit level quickly is crucial for designers to accurately predict front-end-of-line reliability (i.e., hot carrier injection, bias temperature instability, and time dependent dielectric breakdown) and achieve better thermal management. In this paper, we: 1) first propose an analytical model based on multistage thermal network to address effectively the self- and mutual-heating within the device; 2) validate the multistage network and proposed analytical model by COMSOL and SPICE simulation, respectively; and 3) utilize the model to investigate local temperature rise in multifinger and multifin FETs-based inverter and ring oscillator as well as provide thermal-aware IC design guideline for self-heating and reliability optimization. The results show that the analytical multistage thermal model can predict local temperature rise and quantify nonuniform temperature difference in full-frequency range, superior to the lumped thermal model. Moreover, the model can offer quick thermal analysis at the pre-Si stage for reliability prediction and thermal-aware design. [ABSTRACT FROM AUTHOR]

With technology node scaling down to 5 nm, the narrow device geometry confines the material thermal conductivity and further aggravates the self-heating effect in gate-all-around (GAA) transistors. In this paper, we investigate the self-heating of horizontally stacked three-layer GAA nanosheet transistors by 3-D finite-element modeling (FEM) simulation. The anisotropic thermal conductivity of nanosheets with the dependence of silicon thickness and temperature is implemented in the FEM simulator to evaluate thermal behavior accurately. The impact of layout design on thermal properties is investigated comprehensively from single device to device arrays with implication on electrical performance. The results indicate that the width of nanosheet is the key parameter to make the tradeoffs between self-heating and electrical characteristic. Meanwhile, the optimizations of layout design are given to suppress the thermal effects, including self-heating, nonuniformity of temperature, and thermal crosstalk at device level. This paper will provide guidelines for layout design, thermal management, device performance, and thermal-aware reliability prediction in the GAA-stacked structure. [ABSTRACT FROM AUTHOR]