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The large commercial success of multiband multimode 3rd-generation cellular products has driven single-chip integration, SAW-filter reduction and low power consumption. State-of-the-art solutions require quad-band EGSM combined with multiband WCDMA/HSPA receiver diversity and integrated GPS. Compact form factors make single-chip SAW-less solutions highly desirable. A Quad-Band GSM/EDGE-only transceiver was published in [1], and Triple-Band WCDMA-only transceiver solutions were published in [2–4]. This work describes the first multiband WCDMA/HSPA/EGPRS single-chip transceiver with GPS and receiver diversity. This device supports UMTS Bands 1,2,3,4,5,6,8,9,10 and GSM/EDGE 800, 900, 1800, 1900MHz Bands. It is implemented in cost-effective 0.18µm RF CMOS technology and uses a reduced number of TX and RX SAW filters.

This paper describes a 6/sup th/-order continuous-time elliptic low-pass filter fabricated in a 0.8 /spl mu/m 2-poly, 2-metal CMOS process. The magnitude and phase characteristics meet the specification of the analog processor used in CDMA cellular phone system. The direct sample method is used in on-chip tuning circuit and it requires less area and power dissipation than conventional method using PLL. The tuning circuit stabilizes the cut-off frequency of the filter to 630 kHz with a stable external clock. Experimental results show that the filter exhibits 0.5 dB passband ripple and 42 dB stop band attenuation. The whole chip dissipates about 12 mW from a single 3.0 V supply.

This paper presents a low noise 900 MHz voltage controlled oscillator (VCO) implemented in 0.6 /spl mu/m CMOS technology. The VCO based on a 4-stage ring oscillator adopted a new differential delay cell to reduce the phase noise. The measured phase noise is -101 dBc/Hz at 100 kHz offset from the center frequency and comparable to that of LC based integrated oscillators. The measured value is smaller than any other previously reported ones in the ring oscillator VCO's. A prototype frequency synthesizer with this VCO shows phase noise of -117 dBc/Hz at 100 kHz offset. The VCO operates from 750 MHz to 1.2 GHz with a single 3 volt power supply.

This paper presents a salient method to design a low noise clock synthesizer for high-speed data processing applications. The proposed design method optimizes the loop bandwidth by using a discrete-time analysis of a PLL and minimizes the clock synthesizer output jitter. Computer simulation is performed and simulation results strongly support the theoretical analysis. A 900 MHz clock synthesizer is experimentally designed and shows the minimum jitter at the optimum bandwidth obtained from the analysis.

Increasing demand on the broadband data transmission via mobile phones drives standards for the third generation cellular phones. Both wide-band CDMA (WCDMA) and CDMA2000 compliant cellular phones make possible full-bandwidth Internet access. A high level of integration is necessary because of low power and low cost requirements, making CMOS implementation attractive. In the WDMA RF receiver, sensitivity, single-tone desensitization, and intermodulation rejection are the key performance indicators and should be minimized by controlling the parameters such as noise figure (NF), input-referred 3/sup rd/-order intercept (IIP3), gain distributions, and voltage-controlled oscillator (VCO) phase noise. Because of the high data rate supported by the WCDMA standard, more stringent control over the parameters is required. An on-chip VCO is helpful, because it eliminates I/O buffers and reduces substrate noise injection and power consumption.

This paper describes a 1.8-GHz self-calibrated phase-locked loop (PLL) implemented in 0.35-/spl mu/m CMOS technology. The PLL operates as an edge-combining type fractional-N frequency synthesizer using multiphase clock signals from a ring-type voltage-controlled oscillator (VCO). A self-calibration circuit in the PLL continuously adjusts delay mismatches among delay cells in the ring oscillator, eliminating the fractional spur commonly found in an edge-combing fractional divider due to the delay mismatches. With the calibration loop, the fractional spurs caused by the delay mismatches are reduced to -55 dBc, and the corresponding maximum phase offsets between the multiphase signals is less than 0.20. The frequency synthesizer PLL operates from 1.7 to 1.9 GHz and the closed-loop phase noise is -105 dBc/Hz at 100-kHz offset from the carrier. The overall circuit consumes 20 mA from a 3.0-V power supply.