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This paper aims to explore a method about electrocardiogram (ECG) signal denoising based on Hilbert-Huang Transform. The empirical mode decomposition method can decompose the noisy signal into a number of Intrinsic Mode Functions. Energy analysis is conducted on the IMFs to find out the boundary between the noisedominated IMFs and ECG signal dominated IMFs accurately. The most noisy IMFs are denoised by using Donoho soft-threshold denoising method. The denoised high frequency IMFs are added to the low frequency IMFs to reconstruct the original signal. The simulation experiments show that this method is simpler than the wavelet denoising method. It is not necessary to choose wavelet basis or determine the number of layers and the threshold. The proposed method can come close to or achieve the best level of wavelet denoising.

This paper describes a teaching method by Pspice simulation in the course of electric circuits. Pspice's rich and powerful functions provide various methods to analyze circuits. Pspice assisted teaching method can be used at different levels to help students solve problems quickly and efficiently, or help them understand the second-order circuit better, even apply this way to some more complex circuits.

Joint source-channel decoding (JSCD) techniques have been proposed to reduce symbol error rate and bit error rate in decoding a sequence through exploiting the residual redundancy, but these techniques always employ only spatial residual redundancy. In this paper, a new JSCD scheme which exploits both spatial and temporal redundancy in motion vector data (MVD) is proposed. Simulation results show that our proposed scheme leads to obvious improvement over the scheme without using the a priori information of temporal redundancy.

This paper introduces a new I/sub DDT/ test generation method based on the fact that a gate delay may differ from its nominal value. A Bayesian optimization algorithm based on genetic algorithms is utilized for I/sub DDT/ test generation. The paper proposes a fitness function to evaluate the evolution of the test patterns and uses a pseudo-probability method to create the first generation test patterns. The test patterns generated by the new approach are proved to be valid by a waveform simulator based on Boolean processes, even though gate delays are assigned randomly from 50% to 150% of their nominal values, and the number of the evolution generation can be reduced about 25%.