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This paper derives in analytical closed form the feasible pole-placement region of the synchronverter active-power loop (APL) so as to eliminate all trial-and-error effort in parameter tuning. We consider the well-established setting of a reduced third-order APL model with two controller parameters that can be tuned freely. Thus, only two of the three APL poles can be specified independently in hopes of achieving desired system dynamics. Central to the presented derivation is the realization that the two specified poles must represent the dominant mode of the system. Otherwise the actual system dynamics may be dictated by the third unspecified pole, leading to unexpected or undesired dynamic behaviour. Numerical simulations involving the full-order synchronverter dynamical model and a modified New England 39-bus test system validate the analysis and the resulting region within which poles must be placed for actual system dynamics to match desired ones. [ABSTRACT FROM AUTHOR]

Dynamically-controlled optical switches can enable novel functionalities in future high-performance computing and data center systems, including resource allocation and real-time routing. These capabilities can improve system robustness, performance, as well as overall power consumption. Silicon (Si) photonic switch fabrics are capable of nanosecond-scale switching, thus making them potentially attractive for dynamic reconfiguration at data packet rates, which are typically in the GHz range and are made via CMOS-compatible processes for smooth process integration. In this paper, we explore the dynamic control of data signals through an Si photonic switch matrix and demonstrate a programming interface for configuring the switch. Our associated control algorithm is shown to provide the capability for dynamically reallocating the optical power through multicasting for robust operation in case the optical loss changes along a given path. The scheme is shown to operate error-free with 40 Gb/s line rate data streams in a $4\times 4$ Si photonic switch fabric. [ABSTRACT FROM PUBLISHER]

An on-chip error-free 40-Gb/s-aggregated-data-rate link is achieved by transmitting a single wavelength of dual polarization-multiplexed (pol-mux) data at 10 Gb/s through a two-mode mode-division-multiplexing (MDM) chip, with a power penalty of <;5 dB/channel. This is the first system-level experimental demonstration of combining pol-mux with MDM to enhance the performance of an on-chip Si photonics network, illustrating the potential to reduce total system electrical power budget by enabling multiple data channels with a single laser. [ABSTRACT FROM PUBLISHER]

Error-free detection at 1 Gb/s is experimentally demonstrated with an all-Si ion-implanted p-i-n waveguide photodetector operating at 1.9 \mum, and the receiver sensitivity is measured. The responsivity of the device is compared between operation at 1.9 and 1.55 \mum, and a 5 dB drop in responsivity is observed. Simulations show that nearly 25% of this drop is due to the lower confinement of the 1.9 \mum wavelength. Theoretical analysis of the waveguide structure optimized for operation at 1.9 \mum shows that data rates of 10 Gb/s are possible with a loss in sensitivity of only 3 dB compared with operation at 1.55 \mum. [ABSTRACT FROM PUBLISHER]