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We fabricate n-channel silicon bulk FinFET with silicon nitride (Si3N4) high- \kappa , silicon nitride/silicon dioxide dual- \kappa , and silicon dioxide (SiO2) low- \kappa spacers, and compare their performance using measurements and TCAD simulations. While all the three devices show similar dc performance, the ac and transient performance of low- \kappa spacer FinFET is better due to lower parasitic capacitance ( {C}_{\mathrm {par}} ). We show that {C} _{\mathrm {par}} in SiO2 spacer FinFET is about half of that with Si3N4 spacer. When the gate length is scaled, the contribution of C \mathrm {par} compared with the intrinsic capacitance ( C \mathrm {ox} ) increases. For FinFET with Si3N4 spacers, C \mathrm {par}/C \mathrm {ox} increases from 36% at 30-nm gate length to 105% when the gate length is scaled to 10 nm, while for FinFET with SiO2 spacers, the ratio changes from 19% to 55% making the latter more suitable for scaling. For SiO2 spacer FinFET, inverter delay is about 13% and 25% lower than Si3N4 spacer FinFET for gate lengths of 30 and 10 nm, respectively. [ABSTRACT FROM PUBLISHER]

We experimentally demonstrate n-channel bulk FinFET with encased air-gap spacers. Encased air gap in the spacer region is formed by depositing carbon sidewalls, encasing them with silicon nitride (SiN) film and finally removing carbon using mild oxygen plasma. We show that the drive current of air-spacer FinFET is improved by about 40% compared with the baseline bulk FinFET with SiN spacers likely due to enhanced tensile stress in the channel. The parasitic capacitance and ring oscillator delay of FinFET with air-spacers is about 25% and 40% lower compared with that with SiN spacers. [ABSTRACT FROM PUBLISHER]

We demonstrate p-channel gate-source/drain underlapped silicon FinFET with HfO2 high- $\kappa $ spacer and compare it with its counterpart having SiO2 low- $\kappa $ spacer. The HfO2 spacer structure reduces series resistance in the underlap regions due to the large capacitive coupling between the gate and the underlap regions. Both drain current and transconductance of p-channel FinFET are higher than those of the SiO2 spacer device by about $3\times $ when biased in the saturation region, and about $1.6\times $ and $2\times $ , respectively, when biased in the linear region. Subthreshold swing and drain-induced barrier lowering are also improved by incorporating the HfO2 spacer. [ABSTRACT FROM PUBLISHER]

Characterization and modeling of SET/RESET cycling-induced SET-disturb failure time degradation in a tungsten oxide resistive random access memory are performed. We find that write-disturb failure time in a high-resistance state (HRS) cell abruptly degrades by the orders of magnitude after certain SET/RESET cycles. To investigate this new degradation mode, we perform the constant voltage stress in high-resistance state (HRS) to characterize the trap generation in a switching dielectric by measuring a stress-induced leakage current and a low-frequency noise. The constant voltage stress is to emulate high-field stress and, thus, trap creation in SET/RESET cycling. We find that a low-field current in HRS by trap-assisted tunneling in a rupture region gradually increases in both the constant voltage stress and the SET/RESET cycling stress. The high-field stress-generated traps, unlike SET-induced oxygen vacancies, cannot be annihilated by RESET operation and are held responsible for a RESET endurance failure. A 3-D Monte Carlo model based on a percolation concept of oxide breakdown is developed to simulate a SET-disturb failure time. Our model includes both the stress-generated traps and the SET-disturb-induced oxygen vacancies. The model can well explain the observed abrupt and the drastic SET-disturb lifetime degradation, which is attributed to the formation of a conductive percolation path of stress-generated traps. [ABSTRACT FROM AUTHOR]

Using a self-aligned sidewall microcrystalline-silicon (\muc\-Si) dual channel, comprising a sub-50-nm channel width, a novel 3-D stackable maskless embedded metal-gate thin-film-transistor nanowire device was fabricated on top metal using a tungsten gate-stack and trilayered oxide/nitride/oxide gate dielectric. The results of using a charge-transferring mechanism based on the solution-phased pH of a phosphate buffer solution and vascular endothelial growth factor showed that \muc\-Si surfaces exhibit high potential for use in bioelectronics. The device exhibits long-term reliability regarding bioelectronic probing and is as reliable as the commercially available enzyme-linked immunosorbent assay when conducting a targeted, 100-day therapy for ovarian cancer. Thus, the proposed device exhibits potential for use in label-free, economical, and highly reliable lab-on-chip 3-D applications. [ABSTRACT FROM PUBLISHER]

NBTI trapped charge characteristics and recovery mechanisms are examined by a statistical study of individual trapped charge emissions in nanoscale HfSiON/metal gate pMOSFETs. We measure individual trapped charge emission times in NBTI recovery in a large number of devices. The characteristic time distributions of the first three emitted holes are obtained. The distributions can be well modeled by using a thermally-assisted tunnel (ThAT) detrapping model. NBTI trapped charge energy and spatial distributions and its activation energy distribution in the ThAT model are discussed and extracted. Based on the ThAT model and measured result of single-charge induced Vt shifts, we develop a statistical NBTI recovery \Delta Vt evolution model. Our model can well reproduce the temporal evolutions of a \Delta Vt distribution in a number of NBTI stressed nanometer MOSFETs in relaxation. [ABSTRACT FROM AUTHOR]

A new degradation mode with respect to write-disturb failure time due to SET/RESET cycling in a tungsten oxide resistive random access memory is reported. In a crossbar array memory, we find that a write-disturb failure time in high resistance state reduces suddenly by several orders of magnitude after certain SET/RESET cycles. This abrupt degradation is believed due to the creation of a new soft breakdown path in a switching dielectric by cycling stress. Although a memory window still remains after the degradation, the occurrence probability of over-SET state increases significantly. This cycling-induced degradation mode imposes a serious constraint on the number of SET-disturb pulses and thus an endurance cycle number in a resistive switching memory. [ABSTRACT FROM PUBLISHER]

The behavior of random telegraph noise was affected by nickel silicide barrier height engineering in advanced nano-CMOS technologies. Contact resistance fluctuations with magnitude of up to 40% were observed when a Schottky barrier was reduced to 0.2 eV. The large contact resistance instability is attributed to the barrier modification by positive charge trapping and detrapping in a Schottky contact. The prevalence and magnitude of the noise are dependent on the contact area, trap density, trap energy, and the silicide Schottky barrier height. In this letter, we propose a fast method to extract the density of responsible contact traps. [ABSTRACT FROM AUTHOR]

Random telegraph noise (RTN) and negative bias temperature (NBT) stress-induced threshold voltage (Vt) fluctuations in high-\kappa gate dielectric and metal-gate pMOSFETs are investigated. We measured RTN amplitude distributions before and after NBT stress. RTN in poststressed devices exhibits a broader amplitude distribution than the prestress one. In addition, we trace a single trapped charge-induced \Delta Vt in NBT stress and find that the average \Delta Vt is significantly larger than a \Delta Vt caused by RTN. A 3-D atomistic simulation is performed to compare a single-charge-induced \Delta Vt by RTN and NBTI. In our simulation, the probability distribution of a NBT trapped charge in the channel is calculated from the reaction-diffusion model. Our simulation confirms that the NBT-induced \Delta Vt indeed has a larger distribution tail than RTN due to a current-path percolation effect. [ABSTRACT FROM PUBLISHER]