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21 results on '"Cheng, C.-Y."'

1. Gate length scaling beyond Si: Mono-layer 2D Channel FETs Robust to Short Channel Effects

Author

Dorow, C. J., primary, Penumatcha, A., additional, Kitamura, A., additional, Rogan, C., additional, O'Brien, K. P., additional, Lee, S., additional, Ramamurthy, R., additional, Cheng, C. -Y., additional, Maxey, K., additional, Zhong, T., additional, Tronic, T., additional, Holybee, B., additional, Richards, J., additional, Oni, A., additional, Lin, C. -C., additional, Naylor, C. H., additional, Arefin, N., additional, Metz, M., additional, Bristol, R., additional, Clendenning, S. B., additional, and Avci, U., additional

Published
2022
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18. Control of the Growth Regimes of Nanodiamond and Nanographite in Microwave Plasmas.

Author

Cheng, C. Y. and Teii, K.

Subjects
*GROWTH, *CARBON films testing, *NANODIAMONDS, *MICROWAVE plasmas, *DIAMOND powder, *FIELD emission, *GRAPHITIZATION, *MANAGEMENT
Abstract

Moderate-pressure microwave plasmas are used to deposit functional nanomaterials consisting of nanodiamond (ND) and/or nanographite. The growth conditions of ND, carbon nanowalls (CNWs), and ND/CNW composite films are categorized in a process map as functions of substrate temperature and Ar concentration with or without scratching pretreatment using diamond powder. Addition of high fractions of Ar to \CH4 plasmas facilitates the formation of \C2 radicals, which is responsible for decreasing the diamond grain size in ND film and enhancing graphitization into the form of graphitic walls in CNWs. The deposition of ND film is limited by substrate surface condition (scratching and seeding) rather than gas-phase condition, whereas that of CNWs is governed by gas-phase condition. A combination of a \C2-rich plasma with scratching pretreatment results in ND/CNW composite film, which increases the space between the walls favorably for better performance of field emission. Based on the insights into gas-phase and surface processes, the deposition mechanism of ND/CNW composite film is discussed to explore the possibility of controlling nano-arrangement of the walls. [ABSTRACT FROM PUBLISHER]

Published
2012
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19. Investigation and Localization of the SiGe Source/Drain (S/D) Strain-Induced Defects in PMOSFET With 45-nm CMOS Technology.

Author

Cheng, C. Y., Fang, Y. K., Hsieh, J. C., Hsia, H., Sheu, Y. M., Lu, W. T., Chen, W. M., and Lin, S. S.

Subjects
METAL oxide semiconductor field-effect transistors, FIELD-effect transistors, METAL oxide semiconductors, COMPLEMENTARY metal oxide semiconductors, SILICON compounds, GERMANIUM compounds
Abstract

In this letter, for the first time, the defects that are induced from the SiGe strain source/drain (S/D) in PMOSFET with 45-nm CMOS technology were investigated in detail. With the conventional charge pumping and the improved low gate-leakage gated-diode (L²-GD) measurements, we find that the uniaxial compressive stress from SiGe S/D generates a large number of acceptorlike interface states at the gate oxide/extension of S/D interface, thus enhancing the leakage current. Compared to defects that are caused by the relaxed Si1-xGex on the conventional graded Si1-xGex buffer layer, the SiGe S/D experienced results that are more serious. The acceptorlike interface states are suspected to be the Si dangling bonds broken by the stress. A schematic model is proposed to illustrate the effect of the stress comprehensively. [ABSTRACT FROM AUTHOR]

Published
2007
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