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Nonconjugated polymers have been synthesized from maleic anhydride, poly(ethylene glycol), and bisphenol-diglycidyl ether without utilizing any solvent. The polymeric thin films produced by the nonconjugated polymers were spin-coated on ITO coated glass and Si substrates. Self-assembly nanoparticles (1.6–6.2 nm) are observed. It is proposed that the nanoparticle is constructed through a self-assembly process with bisphenol-A aggregates and poly(ethylene glycol) moieties. The photoluminescence spectrum of the polymeric thin film on ITO peaks at near 450 nm that spans from 360 to 610 nm under 266 nm excitation. The polymeric thin film exhibits the excitation-wavelength-dependent photoluminescence that the emission peak shifts toward longer wavelength (about 11 nm) when the excitation wavelength increases from 266 to 325 nm, which is attributed to nanoparticle size distribution. Meanwhile, the substrate-dependent photoluminescence has been also observed that the PL peak of the polymeric thin film spin-coated on Si shows a blue shift (about 9 nm) compared with that on ITO, which probably arises from the dielectric screening. The highest occupied molecular orbital energy of the polymeric thin film is about –9.4 eV. The optical band gap is about 3.28 eV. The nonconjugated polymer is expected to use as a host material in optoelectronic applications.

In this study, the characteristics of Maleic-PEGX-SR3 thin films are investigated. This thin film is expected to use as the light emitting layer of polymer light editting diode (PLED). The effect of solution concentration and annealing temperature on the properties of thin films deposited on glass are examined. Thin films are characterized by photoluminescence (PL), scanning electron microscopy (SEM), UV-vis absorption spectrum (UV-vis), and ultraviolet photoemission spectroscopy (UPS). The PL spectra of the thin films prepared by various solution concentrations on glass peak at ∼ 450 nm. The trend of a red shift in PL spectra is observed with increasing solution concentration. In addition, the PL intensity increases with increasing solution concentration is observed. Optical energy band gap (E g ) is ∼ 3.03 eV. Highest occupied molecular orbital (HOMO) is about 10.55 eV. Lowest unoccupied molecular orbital (LUMO) is about 7.52 eV.

It is proposed that the metal-oxide-semiconductor (MOS) solar cells with sol-gel oxides deposited by spin coating are produced in this study. This sol-gel-derived SiO 2 layer is not very thin and the deviation in the thickness of the sol-gel layer is not slight. In general, the characteristics of MOS solar cells are significantly affected by the thickness of the SiO 2 layer. Particularly, the thermal grown oxide thickness required is less than 2nm for MOS solar cell applications. It is useful for large-scale and large-amount manufacturing that the influence of nonuniformity of oxide thickness on the characteristics of MOS solar cells with sol-gel oxides is reduced. It is observed that the short-circuit current density (J sc ) of 15.56 mA/cm2, the open-circuit voltage (V oc ) of 0.49V, the fill factor (FF) of 0.723 and the conversion efficiency (η%) of 5.44% are obtained by means of the current-voltage (I-V) measurements under AM 1.5 illumination at 25°C in the MOS solar cell with sol-gel oxides.

One-transistor (1T) memory cells with long data retention time is achieved with the modulation of drain current by channel traps. For simple demonstration, poly-Si TFTs are used, and grain boundary traps induced by excimer laser annealing are used as channel traps. The channel length in this work is 6 μm and the extrapolated data retention time can be as long as ~107 s at half of the current window. With the assumption that total number of traps is proportional to device volume and leakage current is proportional to the peripheral areas, retention time is scaled with gate length. For 30 nm devices, retention time is estimated to be ≥ 5×104 s. Compared with the conventional Zero-capacitor random access memory (Z-RAM), the channel trap memory provides better retention characteristics. For practical applications, the new channel trap cell has the same gate structure as logic devices, and can be potentially embedded in SoC platform. Due to the defect tolerance of cell channel and the low-temperature process, the 3D (multi-layer) memory structure by stacking the cells vertically can be potentially implemented more easily than flashtype devices [1]. In principle, the channel traps cells can also be implemented in bulk Si and the localized channel traps can be formed in the scaled devices using implantation techniques. This paper proposes a design of 1T memory cells that utilizes the modulation of drain current by channel traps and offers these advantages: 1. capacitorless structure, 2. long data retention time, 3. excellent endurance characteristics, 4. low power consumption, 5. 3D integration compatibility.