Search

The growing prevalence and computational demands of Artificial Intelligence (AI) workloads has led to widespread use of hardware accelerators in their execution. Scaling the performance of AI accelerators across generations is pivotal to their success in commercial deployments. The intrinsic error-resilient nature of AI workloads present a unique opportunity for performance/energy improvement through precision scaling. Motivated by the recent algorithmic advances in precision scaling for inference and training, we designed RaPiD1, a 4-core AI accelerator chip supporting a spectrum of precisions, namely, 16 and 8-bit floating-point and 4 and 2-bit fixed-point. The 36mm2 RaPiD chip fabricated in 7nm EUV technology delivers a peak 3.5 TFLOPS/W in HFP8 mode and 16.5 TOPS/W in INT4 mode at nominal voltage. Using a performance model calibrated to within 1% of the measurement results, we evaluated DNN inference using 4-bit fixed-point representation for a 4-core 1 RaPiD chip system and DNN training using 8-bit floating point representation for a 768 TFLOPs AI system comprising 4 32-core RaPiD chips. Our results show INT4 inference for batch size of 1 achieves 3 - 13.5 (average 7) TOPS/W and FP8 training for a mini-batch of 512 achieves a sustained 102 - 588 (average 203) TFLOPS across a wide range of applications.

How to accurate predict the topology of a constituted wafer and its warpage would be critical in improving processing reliabilities. Traditionally, Stoney equation has been widely used to correlate film stress and wafer warpage. However, it only works under ideal situation and could be deviated from real situation significantly. Many previous studies thus have been performed to revise the relation but these analytical-based formulations usually take single factor into consideration. In reality, multiple imperfection issues are usually simultaneously existed and pure analytical approach would be too challenging to yield useful results. Instead, data-driven methods such as artificial neural network might be feasible to achieve effective black box mapping to evaluate the problem. Specifically, the stress state of bi-layer structures with thicker, viscoelastic, and multi-layer films are investigated in this work to demonstrate the feasibility. The multilayer perception model is chosen and the effects of thick film, viscoelasticity, and multiple layers on film stress are individually investigated subsequently. Finally, all three factors are simultaneously considered under the same MLP structure and a 99% successful rate can be achieved based on a 5% deviation threshold with 2300 simulation data. Meanwhile, a program is designed to reconstruct and visualize the deformed wafer surface from local curvatures as the preparation for final real 3D reconstitute structure study in the future.

Low-precision computation is the key enabling factor to achieve high compute densities (T0PS/W and T0PS/mm2) in AI hardware accelerators across cloud and edge platforms. However, robust deep learning (DL) model accuracy equivalent to high-precision computation must be maintained. Improvements in bandwidth, architecture, and power management are also required to harness the benefit of reduced precision by feeding and supporting more parallel engines to achieve high sustained utilization and optimize performance within a given product power envelope. In this work, we present a 4-core AI chip in 7nm EUV technology that exploits cutting-edge algorithmic advances for iso-accurate models in low-precision training and inference [1, 2] and aggressive circuit/architecture optimization to achieve leading-edge power-performance. The chip supports fp16 (DLFIoat16 [8]) and hybrid-fp8(hfp8) [1] formats for training and inference of DL models, as well as int4 and int2 formats for highly scaled inference.

A processor core is presented for AI training and inference products. Leading-edge compute efficiency is achieved for robust fp16 training via efficient heterogeneous 2-D systolic array-SIMD compute engines leveraging compact DLFloat16 FPUs. Architectural flexibility is maintained for very high compute utilization across neural network topologies. A modular dual-corelet architecture with a shared scratchpad and a software-controlled network/memory interface enables scalability to many-core SoCs and large-scale systems. The 14nm AI core achieves fp16 peak performance of 3.0 TFLOPS at 0.62V and 1.4 TFLOPS/W at 0.54V.

In this paper, the analysis and implementation of active bleeder for TRIAC dimmable LED driver is presented. The insufficient holding current problem occurs when LED driver is connected to TRIAC dimmer, causing TRIAC dimmer misfire and LED flicker. Therefore, a bleeder circuit is parallel-connected to provide TRIAC enough holding current. In the bleeder, the resistor is usually used to control the amount of current through the bleeder, and cause high power loss on the resistor. A bleeder circuit with an inductor, a capacitor and switches is used to provide TRIAC dimmer extra current to reduce the power dissipation by using a resistor. Finally, the hardware type of the bleeder circuit with input voltage of 90~135V is implemented, and able to applied on the TRIAC dimmable 7.2W LED driver. The bleeder can provide enough holding current, widening the conducting angle of TRIAC dimmer with no flicker and misfire occur.

To increase disk I/O performance, Linux performs prefetching to read more data that is expected to be used in the near future. Nevertheless, the current Linux prefetching architecture is designed specifically for hard disk drives (HDDs). In recent decades, flash-based solid-state drives (SSDs) have been widely deployed in the storage systems, especially as caches forming a multi-tiered storage system, to boost I/O performance. Since the access characteristics of HDDs and SSDs are drastically different, the data prefetching scheme of Linux must be re-designed. Thus, in this paper, we proposed a new data prefetching architecture, called Cross-Layer Adaptive Caching (CLAP), for multi-tiered storage systems. CLAP adaptively determines the prefetching depth by analyzing the degree of data access sequentiality and the characteristics of the accessed storage devices. From the experimental results, CLAP can successfully improve the I/O access performance in multi-tiered storage systems.

A multi-TOPS AI core is presented for acceleration of deep learning training and inference in systems from edge devices to data centers. With a programmable architecture and custom ISA, this engine achieves >90% sustained utilization across the range of neural network topologies by employing a dataflow architecture and an on-chip scratchpad hierarchy. Compute precision is optimized at 16b floating point (fp 16) for high model accuracy in training and inference as well as 1b/2b (bi-nary/ternary) integer for aggressive inference performance. At 1.5 GHz, the AI core prototype achieves 1.5 TFLOPS fp 16, 12 TOPS ternary, or 24 TOPS binary peak performance in 14nm CMOS.

Deep Neural Networks (DNNs) have emerged as a powerful and versatile set of techniques to address challenging artificial intelligence (AI) problems. Applications in domains such as image/video processing, natural language processing, speech synthesis and recognition, genomics and many others have embraced deep learning as the foundational technique. DNNs achieve superior accuracy for these applications using very large models which require 100s of MBs of data storage, ExaOps of computation and high bandwidth for data movement. Despite advances in computing systems, training state-of-the-art DNNs on large datasets takes several days/weeks, directly limiting the pace of innovation and adoption. In this paper, we discuss how these challenges can be addressed via approximate computing. Based on our earlier studies demonstrating that DNNs are resilient to numerical errors from approximate computing, we present techniques to reduce communication overhead of distributed deep learning training via adaptive residual gradient compression (AdaComp), and computation cost for deep learning inference via Prameterized clipping ACTivation (PACT) based network quantization. Experimental evaluation demonstrates order of magnitude savings in communication overhead for training and computational cost for inference while not compromising application accuracy.

A fast two-point measurement methodology, applicable to nano-scale devices, is introduced to separate electron trapping (Not, e) from interface state contributions (Nit) in hot carrier (HC) induced ΔVt in n-type RMG SOI FinFETs. It is shown that Not, e component is comparable to or dominates over Nit for high-Vg (≥ Vd) hot carrier stress (HCS). The time power-law exponent for HC induced Not, e is larger than 0.2, indicating the observed Not, e is partly due to injection of hot carriers instead of purely parasitic PBTI effect caused by the cold carriers.

We reported large size amorphous Indium-Gallium-Zinc-Oxide and Indium-Tin-Zinc-Oxide thin film transistors active-matrix organic light-emitting diode television development history in AUO. The Gen6 threshold voltage uniformity can lower than 1.0V. Amorphous Indium-Tin-Zinc-Oxide thin film transistors show a higher mobility of 33.2 cm 2 /VS. Amorphous 56 inches back channel etch type Indium-Tin-Zinc-Oxide active-matrix organic light-emitting diode television is 1st time revealed. Metal-organic chemical vapor deposition system is used to evaluate the new high mobility material. The side-by-side organic light-emitting diode device is realized by fine metal mask. The dam and fill encapsulation method shows a simple process procedure and highly stability. Ink jet printing is adopted to produce a small size full color panel. By the application of compensation pixel circuit, the panel drove by AUO engine shows an excellent characteristic.

Random telegraph noise (RTN) in high-κ nMOSFETs is directly linked to Positive Bias Temperature Instability (PBTI). For the first time, the correlation between I d - and I g -RTN is clearly observed in high-κ MOSFET. I g -RTN is directly related to physical trapping or de-trapping and the I d -RTN reflects sensitivity to charge trapping as determined by gm, which is confirmed by both experiments and TCAD simulations.

To further device scaling, a new hetero-channel MOS device is considered. A novel Ge/SiGe/Si lateral hetero-channel p- FET that can significantly reduce band-to-band tunnelling (BTBT) leakage, retain high current drivability, and good electrostatics is introduced in this paper. Through detailed BTBT model in PDE simulators the on-current and off current in p- FETs are analyzed. The simulation results show one-order of magnitude reduction (>20) in minimum off current and high drive current. Lateral hetero-channel p-FET provides a promising solution for future highly scaled CMOS technology. Index Terms — SiGe; field effect transistor; BTBT leakage; device scaling

Advanced harmonic balance simulation capabilities have been used to investigate linearity behavior in RF power LDMOS devices with different laterally graded channel doping profiles. Harmonic balance analysis provides relevant device information from device-level simulations and yield performance metrics of RF circuits. The linearity behavior of a simple quasi-1D structures with different graded channel doping profiles was investigated; the analysis was then extended to a more realistic power LDMOS device. The third-order intermodulation distortion product (IM3) reveals the important role of the lateral channel doping in RF power LDMOS. The analysis lays ground-work for device optimization for improved linearity.

In this paper, we proposed an integrated data mining system for patient monitoring with applications on asthma care. In this system, two data mining methods named PBD and PBC are designed for predicting asthma attacks. The main methodology is to extract the significant information of asthma attacks and build classifiers by using users' daily bio-signal records and environmental data. Meanwhile, helpful medical information and suggestions supported by doctors are applied. In this way, the proposed system can predict the chances of asthma attacks and provide patients with the proper medical instructions or health messages. The experimental evaluation results proved that the proposed mechanism is effective and reliable in asthma attack prediction.

In this paper, a wide tuning range switched current-reused VCO for 2.5 GHz and 3.4 GHz WiMAX applications is presented. The frequency bands consist of eight switched sub-bands and cover 2.438-2.971 GHz and 3.104-3.786 GHz. The measured phase noise at 100-kHz and 1-MHz offset frequencies are -101.47 and -119.28 dBc/Hz at lower band and -103.99 and 122.28 dBc/Hz at higher band. With 1.5V voltage supply, the power consumption of the VCO is 2.886 mW. This circuit was fabricated by TSMC 0.18 m CMOS process.

For a practical operation, multiple groups of Web servers with different performance may coexist in a Web cluster. In this paper, we propose a quantitative method based on a typical M/G/1 queuing model to analyze and equalize the service performance of multiple groups of Web servers. We also propose a two-pass method for providing uniform distribution of Web documents to the multiple grouping of a Web cluster system. In addition to the primary function of maintaining a load balance of Web requests, we introduce the extra pass to distribute the complement parts of the Web documents to the disks of the other servers. Usually, these hidden documents are not used for normal operation. If one of the servers is down, these servers can be replaced by the spare server that has the spare copy of the Web documents by the allocation of the second pass.