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An unexpected POR (Power-on Reset) may lead to system unstable or hanging-up during the booting. This paper proposed a new reset IC structure to monitor system power during power ramp-up. For system design, this chip contains hysteresis input voltage, power delay control, output enable, power good signal, and LVRC (Low Voltage Reset Circuit). Finally, the proposed IC is designed with TSMC 0.35µm 2P4M process. The chip specifications are listed below: 3.3V +/− 10% as input power, 1.5∼5V as analog input signal, 15∼30mV as hysteresis input voltage, 2.7∼2.8V as startup voltage of LVRC, and 40mW as chip power consumption. It can be applied to most current mobile device.

This paper presents low-complexity digital sample rate conversion (SRC) circuit architecture with arbitrary factor conversion ratio. The strategy in deciding SRC system parameters is given to guarantee that both the anti-imaging and the anti-aliasing requirements can be satisfied. The significant reduction in the complexity of the proposed structure allows simple VLSI implementation without affecting the performance. A parallel cascaded integrator comb (CIC) filter circuit without high intermediate sample rate and a multiplier-less linear interpolator are also developed to obtain a cost-effective and high-speed SRC circuit.