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Memristor crossbar arrays are used in a wide range of in-memory and neuromorphic computing applications. However, memristor devices suffer from non-idealities that result in the variability of conductive states, making programming them to a desired analog conductance value extremely difficult as the device ages. In theory, memristors can be a nonlinear programmable analog resistor with memory properties that can take infinite resistive states. In practice, such memristors are hard to make, and in a crossbar, it is confined to a limited set of stable conductance values. The number of conductance levels available for a node in the crossbar is defined as the crossbar’s resolution. This paper presents a technique to improve the resolution by building a super-resolution memristor crossbar with nodes having multiple memristors to generate $r$ -simplicial sequence of unique conductance values. The wider the range and number of conductance values, the higher the crossbar’s resolution. This is particularly useful in building analog neural network (ANN) layers, which are proven to be one of the go-to approaches for forming a neural network layer in implementing neuromorphic computations. [ABSTRACT FROM AUTHOR]

Several results on instability in nonhomogeneous architectures able to generate Turing patterns are presented. The approach makes use of the continuity theorem regarding the dependence of polynomial roots on coefficients and of the root-locus techniques for small, and large parameter deviations from their homogeneous values, respectively. The results are valid for any linearized nonhomogeneous discrete model capable of generating Turing patterns. [ABSTRACT FROM PUBLISHER]

This work presents a detailed study of the nonlinear dynamics of a tantalum oxide memristor recently fabricated at Hewlett Packard Labs. Our investigations uncover direct current, quasi-static, and alternating current behavior of the nanodevice. A thorough study of the dynamics emerging in the nanoscale element under various input/initial condition combinations reveals a fundamental property of the tantalum oxide device, which was unnoticed so far. The initial condition has no effect on the steady-state operation of the memristor under non-zero input. This property, known as fading memory in system theory, implies the uniqueness of asymptotic behavior of the memristor. The progressive input-induced memory erase phenomenon is solely determined by the switching dynamics of the nanodevice, mathematically described by the state evolution function, which governs the rate of evolution of the memristor state. A constant-sign DC input will activate on or off switching dynamics only. Consequently, due to the limited on/off memductance ratio, the memristor will asymptotically attain a fully-conducting or highly-resistive state, irrespective of the initial condition. Most interestingly, under AC periodic excitations, it is the pronounced asymmetry in the state dependence of on and off switching processes which is at the basis of the reported history erase effect. It is important to point out that this novel fading memory phenomenon does not compromise the nonvolatile behavior of the nanostructure. In fact, despite the device may be stimulated so as to forget its past history, it still has a continuum of analog nonvolatile memory states. [ABSTRACT FROM PUBLISHER]

As the limits of transistor technology are approached, feature size in integrated circuit transistors has been reduced very near to the minimum physically-realizable channel length, and it has become increasingly difficult to meet expectations outlined by Moore’s law. As one of the most promising devices to replace transistors, memristors have many excellent properties that can be leveraged to develop new types of neural and non-von Neumann computing systems, which are expected to revolutionize information-processing technology. This survey provides a comparative overview of research progress on memristors. Different memristor synaptic devices are classified according to stimulation patterns and the working mechanisms of these various synaptic devices are analyzed in detail. Crossbar-based memristors have demonstrated advantages in physically executing vector-matrix multiplication and enabling highly power-efficient and area-efficient neuromorphic system designs. The extensive uses of crossbar-based memristors cover in-memory logic, vector-matrix multiplication, and many other fundamental computing operations. Furthermore, memristor-based architectures for efficient neural network training and inference have been studied. However, memristors have non-ideal properties due to programming inaccuracies and device imperfections from fabrication, which lead to error or mismatch in computed results. To build reliable memristor-based designs, circuit-level, algorithm-level, and system-level solutions to memristor reliability issues are being studied. To this end, state-of-the-art realizations of memristor crossbars, crossbar-based designs, and peripheral circuitry are presented, which show both promising full-system inference accuracy and excellent power efficiency in multiple tasks. Memristor in-situ learning benefits from high energy efficiency and biologically-imitative characteristics, which are conducive to further realizing hardware acceleration of cognitive learning. At present, the learning and training processes of brain-like networks are complex, presenting great challenges for network design and implementation. [ABSTRACT FROM AUTHOR]

We present a compact, continuous, and numerically stable version of a tantalum oxide (TaOx) memristor model which can be employed for robust and reliable simulations of large scale memristor based circuits. The original model contains a piecewise differentiable function in the memductance expression and discontinuous step functions in the state equation. Additionally, the original model does not set a proper upper bound for the state variable and may admit blowing up solutions due to an exponential power term, preventing the use of it for numerically reliable simulations. Considering these drawbacks, we modify the original model so as to i) simplify the memductance function while removing its piecewise differentiable nonlinearity, ii) include a proper window function for the ON state dynamics, which is missing in the original model, iii) modify and bound the exponential power term to prevent an uncontrollable blow-up of the solutions, and iv) apply a process called unification, allowing us to remove the step functions inherent in the model, which is a novelty in state-limited memristor models. We validate the accuracy of the proposed model via DC and transient simulations, dynamic route map analysis and a Spice implementation of an anti-series configuration, showing the applicability of the model. [ABSTRACT FROM AUTHOR]

Discharge lamps can be classified as high-pressure and low-pressure lamps, which operate under different scientific principles. They have exhibited the well-known fingerprints of memristors. This paper describes the mathematical models of both of high- and low-pressure discharge lamps based on their respective physical nature and behaviors, and then explains how these models can be unified into a generalized mathematical framework that confirms their memristor characteristics. Practical and theoretical results from high-pressure and low-pressure lamps are included to illustrate their 3 fingerprints of the memristor characteristics. The results indicate that gas discharge lamps are not ideal but volatile memristors. [ABSTRACT FROM AUTHOR]

This paper presents a circuit-theoretic analysis of a NbO2-Mott memristor fabricated at Hewlett-Packard Labs. It investigates mechanisms behind the origin of complexity based on local activity, which characterizes the behavior of this outstanding nanodevice. We propose an accurate, particularly simplified version of a recently introduced physical model suitable for large-scale circuit simulations. Following the concept of local activity, we then conduct a small-signal circuit-theoretic derivation of the impedance and associated small-signal equivalent circuit elements to analyze device stability and frequency response. Finally, our analysis reveals locally active operating regions, as well as regions where the device dynamics are positioned on the edge of chaos. The latter regions are crucial for designing bio-inspired computing systems. [ABSTRACT FROM AUTHOR]

We present and experimentally validate two minimal compact memristive models for spiking neuronal signal generation using commercially available low-cost components. The first neuron model is called the Memristive Integrate-and-Fire (MIF) model, for neuronal signaling with two voltage levels: the spike-peak, and the rest-potential. The second model MIF2 is also presented, which promotes local adaptation by accounting for a third refractory voltage level during hyperpolarization. We show both compact models are minimal in terms of the number of circuit elements and integration area. Using the MIF and MIF2 models, we postulate the design of a memristive solid-state brain with an estimation of its surface area and power consumption. Analytical projections show that a memristive solid-state brain could be realized within (i) the surface area of the median human brain, 2,400cm2, (ii) the same volume of the median human brain, and (iii) a total power budget of approximately 20 W using a 3.5 nm technology. Distinct from the past decade of memristive neuron literature, our benchmarks are attained using generic commercially available memristors that are reproducible using off-the-shelf components. We expect this work can promote more experimental demonstrations of memristive circuits that do not rely on prohibitively expensive fabrication processes. [ABSTRACT FROM AUTHOR]

Neuromorphic computing can solve computationally hard problems with energy efficiencies unattainable for von Neumann architectures. A locally-active memristor, which possesses the capability to amplify infinitesimal fluctuations in energy and can be used to generate neuromorphic behaviors, is a natural candidate for constructing an electronic equivalent of biological neurons. This paper identifies some unknown neuromorphic dynamics of the Chua corsage memristor (CCM), and shows that the CCM, when biased at the edge of chaos domain, can exhibit rich dynamics of biological neurons. Using Chua’s theories of local activity and edge of chaos, we demonstrate that under the destabilizing of the input voltage and the circuit parameters (inductance or capacitance), two CCM-based circuits can produce thirteen types of neuromorphic behaviors either on, or near the edge of chaos domain via supercritical or subcritical Hopf bifurcation. In addition, we give the conditions to test the edge of chaos of the CCM and the CCM-based circuit only by using the poles and the zero of their admittance functions. [ABSTRACT FROM AUTHOR]

In the memristive version of a standard space-invariant Cellular Nonlinear Network, each cell accommodates one first-order non-volatile memristor in parallel with a capacitor. In case, the resistance switching memory may only undergo almost-instantaneous switching transitions between two possible resistive states, acting at any time, as either the on or the off resistor, the processing elements effectively operate as first-order dynamical systems, and the classical Dynamic Route Map technique may be applied to investigate their operating principles. On the contrary, in case the memristors experience smooth conductance changes, as the bioinspired array implements memcomputing paradigms, each cell truly behaves as a second-order dynamical system. The recent extension of the Dynamic Route Map analysis tool to systems with two degrees of freedom constitutes a powerful technique to investigate the nonlinear dynamics of memristive cellular networks in these scenarios. This paper exploits this system-theoretic technique, called Second-Order Dynamic Route Map, to introduce a novel systematic procedure to design memristive arrays, in which a given memcomputing task is executed by ensuring that, depending upon the network inputs and initial conditions, the analogue dynamic routes of the states of the processing elements, namely capacitor voltages and memristor states, asymptotically converge toward pre-defined stable equilibria. [ABSTRACT FROM AUTHOR]

If the memristor, used in each cell of a memristive variant of the standard space-invariant Cellular Nonlinear Network (CNN), undergoes analogue memductance changes, the processing element operates as a second-order system. The Dynamic Route Map (DRM) technique, applicable to investigate first-order systems only, is no longer relevant. In this manuscript, a recently introduced methodology, generalizing the DRM technique to second-order systems, is applied to the models of Memristor CNN (M-CNN) cells, accomodating dynamic memristors. This allows to gain insights into the operating principles of these cellular structures, which make computations through the evolution of their states toward prescribed equilibria. Our analysis uncovers all possible local and global phenomena, which may emerge in the cell phase space under zero offset current for any self-feedback synaptic weight. Under these hypotheses, the dynamics of the M-CNN cell may significantly differ from those of a standard space-invariant CNN counterpart. The insertion of an offset current into each cell endows it with further properties, including monostability. The analysis method is used to demonstrate how a non-autonomous memristive array exploits the capability of its cells to feature monostability or bistability, depending upon the respective offset currents, to compute the element-wise logical AND between two binary images. [ABSTRACT FROM AUTHOR]

This paper presents the theory of a novel memcomputing paradigm based upon a memristive version of standard Cellular Nonlinear Networks. The insertion of a nonvolatile memristor in the circuit of each cell endows the dynamic array with the capability to store and retrieve data into and from the resistance switching memories, obviating the current need for extra memory blocks. Choosing the parameters of each cell circuit so that the memristors may undergo solely sharp transitions between two states, each processing element may be approximately described at any time as one of two first-order systems. Under this assumption, the classical Dynamic Route Map may be employed to synthesise and analyse the data storage and retrieval genes. A new system-theoretic methodology, called Second-Order Dynamic Route Map, is also introduced for the first time in this paper. This technique allows to study the operating principles of arrays with second-order processing elements, as is the case, in the proposed network, if the set up of cell circuit parameters induces analogue memristive dynamics. This paper shows how the novel tool may be adopted to investigate the operating mechanisms of a cellular array with second-order cells, which compute the element-wise logical OR between two binary images. [ABSTRACT FROM AUTHOR]

The formation of ordered structures, in particular Turing patterns, in complex spatially extended systems has been observed in many different contexts, spanning from natural sciences (chemistry, physics, and biology) to technology (mechanics and electronics). In this paper, it is shown that the use of memristors in a simple cell of a spatially-extended circuit architecture allows us to design systems able to generate Turing patterns. In addition, the memristor parameters play a key role in the selection of the type and characteristics of the emerging pattern, which is also influenced by the initial conditions. The problem of finding the regions of parameters where Turing patterns may emerge in the proposed cellular architecture is solved in an analytic way, and numerical results are shown to illustrate the system behavior with respect to its parameters. [ABSTRACT FROM PUBLISHER]

This paper reports on the dynamic behavior of dual coupled memristors (MRs) in serial and parallel connections in consideration of polarity combination and coupling strength. Based on the constitutive relations, two flux coupled MRs are adopted for demonstration to theoretically exhibit the variation of memductance in terms of flux, charge, voltage, and current. The coupled MRs are also serially connected with a regular resistor to further explore its memristive behavior. Theoretical analysis reported in this paper is confirmed via a simulation study, and then an experimental investigation is carried out using a practical circuit emulating the dual coupled MRs. Good agreement between experimental and simulation results confirms that dual coupled MRs in composite connections behave as a new MR with higher complexity. [ABSTRACT FROM AUTHOR]

Memristor-based circuit architecture for multilayer neural networks is proposed. It is a first of its kind demonstrating successful circuit-based learning for multilayer neural network built with memristors. Though back-propagation algorithm is a powerful learning scheme for multilayer neural networks, its hardware implementation is very difficult due to complexities of the neural synapses and the operations involved in the learning algorithm. In this paper, the circuit of a multilayer neural network is designed with memristor bridge synapses and the learning is realized with a simple learning algorithm called Random Weight Change (RWC). Though RWC algorithm requires more iterations than back-propagation algorithm, we show that a circuit-based learning using RWC is two orders faster than its software counterpart. The method to build a multilayer neural network using memristor bridge synapses and a circuit-based learning architecture of RWC algorithm is proposed. Comparison between software-based and memristor circuit-based learning are presented via simulations. [ABSTRACT FROM AUTHOR]

This paper illustrates that for a device to be a memristor it should exhibit three characteristic fingerprints: 1) When driven by a bipolar periodic signal the device must exhibit a “pinched hysteresis loop” in the voltage-current plane, assuming the response is periodic. 2) Starting from some critical frequency, the hysteresis lobe area should decrease monotonically as the excitation frequency increases, and 3) the pinched hysteresis loop should shrink to a single-valued function when the frequency tends to infinity. Examples of memristors exhibiting these three fingerprints, along with non-memristors exhibiting only a subset of these fingerprints are also presented. In addition, two different types of pinched hysteresis loops; the transversal (self-crossing) and the non-transversal (tangential) loops exhibited by memristors are also discussed with its identification criterion. [ABSTRACT FROM PUBLISHER]

A memristor emulator which imitates the behavior of a \ TiO2 memristor is presented. Our emulator is built from off-the-shelf solid state components. To develop real world memristor circuit applications, the emulator can be used for breadboard experiments in real time. Two or more memristor emulators can be connected in serial, in parallel, or in hybrid (serial and parallel combined) with identical or opposite polarities. With a simple change of connection, each memristor emulator can be switched between a decremental configuration or an incremental configuration. The hardware and spice simulation of the proposed emulator showed promising results that provides an alternative solution of hp∼\ TiO2 memristor model in real circuit. [ABSTRACT FROM AUTHOR]

A pulse-based programmable memristor circuit for implementing synaptic weights for artificial neural networks is proposed. In the memristor weighting circuit, both positive and negative multiplications are performed via a charge-dependent Ohm's law (). The circuit is composed of five memristors with bridge-like connections and operates like an artificial synapse with pulse-based processing and adjustability. The sign switching pulses, weight setting pulses and synaptic processing pulses are applied through a shared input terminal. Simulations are done with both linear memristor and window-based nonlinear memristor models. [ABSTRACT FROM AUTHOR]

A very-high-performance Viterbi decoder with a circularly connected two-dimensional analog cellular neural network (CNN) cell array is disclosed. In the proposed Viterbi decoder, the CNN cells with nonlinear unilateral connections are implemented with electronic circuits at nodes on a trellis diagram. The circuits are circularly connected, forming a cylindrical shape so that the cells of the last stage are connected to those of the first stage. Unilateral connections guide the information to flow circularly around the cylindrical surface. Such configuration enables the conceptually infinite length of the trellis diagram to be reduced to a circuit of limited size. The analog circuits does not require any analog-digital converters, which is the major cause of high power consumption and the quantization error. With the parallel analog processing structure, its decoding speed becomes very high. Also, the decoding mechanism using triggering wave of the CNN circuit does not require the path memory. Circuits for the proposed structure have been designed with HSPICE. Features of the proposed Viterbi decoder are compared with those of the conventional digital Viterbi decoder. [ABSTRACT FROM AUTHOR]