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Due to high performance and low power consumption, heterogeneous processors are widely used in many real-time systems. In these systems, if tasks are not completed before deadline, it will cause disastrous consequences, and thus it is important to provide fault-tolerance. This paper proposes a novel, adaptive and transient fault-tolerant scheduling algorithm to solve the fault-tolerant problem in heterogeneous real-time systems, aiming to improve system reliability within a given deadline. Since task replication is efficient in improving system reliability, the proposed algorithm supports multiple replicas for each primary task and allows the primary tasks and their replicas to be scheduled on the same processor to increase reliability and lower latency. Also, the algorithm can dynamically adjust the number of replicas for each task to accommodate the deadline and ensure higher reliability. Simulated results show that the proposed algorithm can achieve higher reliability in comparison with existing and related fault-tolerant algorithms. To be specific, the proposed algorithm can obtain the reliability of 89.37% whereas the two existing algorithms DB-FTSA and FTSA obtain the reliability of 47.05% and 84.75% for the benchmark of sixty tasks, respectively, to be detailed in Fig. 4 in experiment.

The co-existence of activation sparsity and model sparsity in convolutional neural network (CNN) models makes sparsity-aware CNN hardware designs very attractive. The existing sparse CNN accelerators utilize intersection operation to search and identify the key positions of the matched entries between two sparse vectors, and hence avoid unnecessary computations. However, these state-of-the-art designs still suffer from three major architecture-level drawbacks, including 1) hardware cost for the intersection operation is high; 2) frequent stalls of computation phase due to strong data dependency between intersection and computation phases; and 3) unnecessary data transfer incurred by the explicit intersection operation. By leveraging the knowledge of the complete sparse 2-D convolution, this paper proposes two key ideas that overcome all of the three drawbacks. First, an implicit on-the-fly intersection is proposed to realize the optimal solution for intersection between one static stream and one dynamic stream, which is the case for sparse neural network inference. Second, by leveraging the global computation structure of 2--D convolution, we propose a specialized computation reordering to ensure that the activation is only transferred if necessary and only once. Based on these two key ideas, we develop GoSPA, an energy-efficient high-performance Globally Optimized SParse CNN Accelerator. GoSPA is implemented with CMOS 28nm technology. Compared with the state-of-the-art sparse CNN architecture, GoSPA achieves average 1.38X, 1.28X, 1.23X, 1.17X, 1.21X and 1.28X speedup on AlexNet, VGG, GoogLeNet, MobileNet, ResNet and ResNeXt workloads, respectively. Also, GoSPA achieves 5.38X, 4.96X, 4.79X, 5.02X, 4.86X and 2.06X energy efficiency improvement on AlexNet, VGG, GoogLeNet, MobileNet, ResNet and ResNeXt, respectively. In more comprehensive comparison including DRAM access, GoSPA also shows significant performance improvement over the existing designs.

Low delay is an important issue in a variety of applications on heterogeneous computing platforms. A great number of algorithms including heuristics as well as metaheuristics have been designed to minimize the completion time (i.e., makespan) of applications and achieved good results. However, the demand of high performance never stops. In this paper, we propose a new and efficient Ant-Colony based Low Delay Scheduling (ACLDS) algorithm to minimize the makespan of applications which can form directed acyclic graphs and are executed on a heterogeneous system. Simulated results show that our proposed algorithm is highly efficient in reducing makespan in comparison with state-of-the-art scheduling algorithms. For instance, the reduction ratio can be up to 15.2174% for a Fast Fourier Transform (FFT) benchmark.

Placement plays a key role in determining FPGA circuit characteristics. Meanwhile, its long computation time is an important factor that makes the flexibility of FPGA computing much less competitive than software compiling. One observation is that there is an increasing need for designs with regularity. A particular example is systolic array-based neural network circuit design. In this work, FPGA placement exploiting design regularity is studied. For neural network designs with systolic arrays, our proposed regularity-aware approach achieves 2X to 28X speed up versus Versatile Place and Route (VPR) with limited circuit performance loss. At the same time, its solution quality is almost perfectly correlated with VPR and thus renders its role for early prototyping.

Gaussian process (GP) is a popular machine learning technique that is widely used in many application domains, especially in robotics. However, GP is very computation intensive and time consuming during the inference phase, thereby bringing severe challenges for its large-scale deployment in real-time applications. In this paper, we propose two efficient hardware architecture for GP accelerator. One architecture targets for general GP inference, and the other architecture is specifically optimized for the scenario when the data point is gradually observed. Evaluation results show that the proposed hardware accelerator provides significant hardware performance improvement than the general-purpose computing platform.

DNN has achieved state-of-the-art performance in MIMO detection problem. However, the deep and large model is hard to deploy to resource constrained platforms. In this work, we propose to provide a sparse DNN model for MIMO detection using permuted diagonal matrices. As a result, our model is with low complexity and doesn't have indexing overhead like other sparsity method. Experiment shows that our method can achieve high sparsity while maintaining the model performance.

Tensors, as the multidimensional generalization of matrices, are naturally suited for representing and processing high-dimensional data. To date, tensors have been widely adopted in various data-intensive applications, such as machine learning and big data analysis. However, due to the inherent large-size characteristics of tensors, tensor algorithms, as the approaches that synthesize, transform or decompose tensors, are very computation and storage expensive, thereby hindering the potential further adoptions of tensors in many application scenarios, especially on the resource-constrained hardware platforms. In this paper, we propose a reduced-complexity SVD (Singular Vector Decomposition) scheme, which serves as the key operation in Tucker decomposition. By using iterative self-multiplication, the proposed scheme can significantly reduce the storage and computational costs of SVD, thereby reducing the complexity of the overall process. Then, corresponding hardware architecture is developed with 28nm CMOS technology. Our synthesized design can achieve 102GOPS with 1.09 mm2 area and 37.6 mW power consumption, and thereby providing a promising solution for accelerating Tucker decomposition.

Learning deep representations have been widely used in action recognition task. However, the features extracted by deep convolutional neural networks (CNNs) have many redundant information. This paper aims to discover the relevance between temporal features extracted by CNNs. Different fromTemporal Segment Networks (TSN) to randomly select video clips. Based on the matrix-based Renyi’s α-entropy, we estimate the mutual information between temporal domain features. Through our experiments, we propose an adaptive temporal segmentation scheme to represent the entire videos. We also combine the features of RGB and optical flow frames extracted by 3D ConvNets to verify the complementary information between them. We show that the proposed approach achieves 94.4 and 72.8 percent accuracy, in the UCF- 101 and HMDB-51 datasets.

Solid state drive (SSD) as a fast storage device has been playing an important role across many applications from mobile computing to large distributed systems in recent years. However, the performance of the SSD can be degraded tremendously due to the intrinsic properties of NAND-based flash memory including limited erase cycles and asymmetric write and erase operations. Previous works separated hot/cold data into different blocks in order to improve SSD performance. “Hotness” is typically defined as the cumulative update frequencies of pages. However, we believe that an additional new parameter, average update time interval, should also be considered into the “hotness” definition associated with the update frequency. Moreover, to adaptively classify hot/cold data, a machine learning algorithm is applied to better accommodate the dynamically changed I/O access patterns of traces. In this paper, a machine learning (ML) based SSD management called HAML-SSD is proposed. The purpose of applying the ML algorithm is to dynamically cluster the data with similar “hotness” based on a new definition of “hotness”. Thus, a two-dimension clustering algorithm is used for storing the pages categorized into the same cluster within the same block. Moreover, to obtain reasonable training time, a specific hardware component called HAML-unit is designed in the SSD. Finally, the experimental results indicate that the HAML-SSD decreases the response time around 26.3% – 57.7% compared to previous works with the evaluation of real traces.

Tensor provides a brief and natural representation for large-scale multidimensional data by way of appropriate low-rank approximations, thus we can discover significant latent structures of complex data and generalize data representation. To date, tensor has gained tremendous success in various science and technology fields, especially in machine learning and big data applications. However, tensor computation, especially tensor decomposition, is usually expensive due to the inherent large-size characteristic of tensors, and hence would potentially hinder their future wide deployment. In this paper, we develop a hardware architecture to accelerate tensor singular value decomposition (t-SVD), which is a new tensor decomposition technique that has been successfully applied to high-dimensional data classification and video recovery. Specifically, design consideration of each key computing unit is analyzed and discussed. Then, the proposed t-SVD hardware architecture is implemented and synthesized using CMOS 28nm technology. Comparison with real-world CPU-based implementations shows that the proposed hardware accelerator is expected to provide average 14× speedup on various t-SVD workloads.

Neural network has been applied into MIMO detection problem and has achieved the state-of-the-art performance. However, it is hard to deploy these large and deep neural network models to resource constrained platforms. In this paper, we impose the circulant structure inside neural network to generate a low complexity model for MIMO detection. This method can train the circulant structured network from scratch or convert from an existing dense neural network model. Experiments show that this algorithm can achieve half the model size with negligible performance drop.

Practical Byzantine Fault Tolerance (PBFT) is a deterministic consensus algorithm, which is widely used in blockchain due to the advantage of no forks. However, PBFT still has some problems, such as not being suitable for dynamic networks, requiring large communication overhead, and not being able to identify Byzantine nodes. Therefore, we propose Extensible-PBFT (EPBFT) consensus algorithm, it can take different steps to reach consensus according to the network environment of the system. Firstly, we add the election of consensus nodes based on verifiable random function (VRF), which makes EPBFT suitable for dynamic networks. Then, we modify the consistency protocol so that EPBFT can reach consensus with less communication in a stable network, and it can also identify Byzantine nodes and reduce confirmation latency. Finally, we simplify the checkpoint protocol and the view-change protocol, reducing the time and communication overhead they require.

Nowadays, data has been more intensive and collaborative than in the past. In this paper, we propose a new accountable data sharing scheme based on blockchain and SGX, in which data subscription undeniable. By utilizing blockchain, the records of users data sharing acts are tamper-resistant, and our scheme no longer needs a trusted third party. SGX ensures the confidentiality of sharing data.

Blockchain is one of the hot research technologies recently. Blockchain-based distributed ledger requires that all the transactions are public and transparent such that the transactions information is recorded on the chain, which may easily cause the privacy disclosure and other problems. Therefore, in order to preserve users' privacy, the transaction amount should be hidden. The common method is homomorphic commitment. When verifying the legitimacy of a transaction, using the range proof protocol to verify that the transaction amount is non-negative. This paper studied and summarized the range proof protocol based on zero-knowledge proof. We discussed the definition of range proof, the research results, the classification of algorithm, the security and efficiency for each algorithm. This paper discussed further directions for the future research.

Blockchain is a specific type of distributed ledger with the features of high transparency and publicly verifiable which may threaten users' data privacy. Due to this concern, we propose a blockchain-based privacy protection identity authentication scheme in this paper. On the one hand, we take advantage of the decentralized feature of blockchain to safely store the hash value of users' identity information in the block of the blockchain, so that these information cannot be tampered and can be verified by the verifier. On the other hand, we introduce a set of key derivation algorithms into the scheme to provide anonymity and unlinkability. The scheme is applicable to scenarios with unified authentication and information privacy protection requirements.

High-resolution scene classification is a fundamental yet challenging problem due to rich image variations in viewpoint, object pose and spatial resolution, etc, which results in large within-class diversity and high between-class similarity. In the paper we focus on tackling the problem of how to learn appropriate feature representation for high-resolution scene classification. To achieve better scene representation, we proposed a combined CNN feature learning framework in multi-scale multi-layer based Gaussian coding (mSmL-Gcoding) manner. In addition, a novel feature coding with Gaussian descriptor is introduced to enhance the discriminative ability of CNN features. Experimental results on two publicly available challenging scene datasets validated that the effectiveness of our method and found it compared favorably with state-of-the-arts.

To improve the reliability of heterogeneous realtime system, researchers often use task replication technology to achieve fault tolerance and improve system reliability. At the same time, real-time tasks in heterogeneous systems need to be completed within very strict time constraints. Usually, reducing time and improving reliability are two conflict factors. In order to balance these two factors, we propose a novel scheduling algorithm-adaptive fault-tolerant scheduling algorithm (AFTSA). The algorithm first generates a dynamic number of replicas for each real-time task according to given deadlines, and then allocate these tasks to appropriate processors to achieve high reliability under time constraints. Experimental results show that our proposed algorithm improves the reliability on average by 26.9% and 30.0% as compared with the existing DB-FTSA and FTSA algorithms while meeting the time constraint, respectively.

Deep neural networks (DNNs) have emerged as an important artificial intelligence technique. However, the computation-intensive and storage-intensive DNNs pose severe challenges on efficient execution over the underlying hardware platform. In this paper we propose to impose Toeplitz structure on DNN models to achieve high compression ratio with negligible performance loss. Accordingly, the hardware performance can be significantly improved after performing model compression. We evaluate the proposed approach on speech recognition and implement the corresponding compressed model on FPGA. Experimental results show that our approach enables high hardware performance while retaining high task performance.

Error-correcting codes are very important in modern communication systems. In this paper, we investigate efficient reduced-complexity deep neural network (DNN)-aided channel decoders. Specifically, we leverage DNN training to obtain individual scaling parameters for normalized min-sum algorithms, thereby leading to much faster convergence for the same target bit error rate (BER). Also, we propose to compress the DNN-aided channel decoders via weight sharing. A case study on DNN-aided BCH decoders is investigated. Simulation results and hardware complexity analysis show that our method can reduce 2.59 times of memory cost than non-compressed DNN-aided BCH decoders. Meanwhile, compared to the conventional BCH decoders, our method can improve convergence rate by 6 times with similar decoding performance.

Among various machine learning techniques, K-Nearest Neighbor (KNN) has been widely exploited for many artificial intelligence applications. However, due to the intensive use of multiplications during its computing procedure, KNN algorithm is typically computation-intensive and thereby posing severe challenge for its efficiency in hardware performance in terms of area and power consumption. To address this challenge, this paper proposes to design an area-efficient low-power stochastic KNN hardware accelerator. By leveraging stochastic computing (SC) technique, the basic computation components of KNN classifier are replaced by simple stochastic logic circuits such as XNOR and MUX gate. Moreover, we propose a low-cost architecture for binary-to-stochastic (B-to-S) interface and develop an Approximate Parallel Accumulator (APA) for stochastic-to-binary (S-to-B) module, which can further improve the hardware performance for the stochastic design. Experimental results demonstrate that the proposed stochastic KNN design achieves higher area efficiency and lower power consumption as compared to the non-stochastic design. Also, it remains high task accuracy with negligible performance loss.

Deep neural network (DNN) has emerged as the most important and popular artificial intelligent (AI) technique. The growth of model size poses a key energy efficiency challenge for the underlying computing platform. Thus, model compression becomes a crucial problem. However, the current approaches are limited by various drawbacks. Specifically, network sparsification approach suffers from irregularity, heuristic nature and large indexing overhead. On the other hand, the recent structured matrix-based approach (i.e., CirCNN) is limited by the relatively complex arithmetic computation (i.e., FFT), less flexible compression ratio, and its inability to fully utilize input sparsity. To address these drawbacks, this paper proposes PermDNN, a novel approach to generate and execute hardware-friendly structured sparse DNN models using permuted diagonal matrices. Compared with unstructured sparsification approach, PermDNN eliminates the drawbacks of indexing overhead, non-heuristic compression effects and time-consuming retraining. Compared with circulant structure-imposing approach, PermDNN enjoys the benefits of higher reduction in computational complexity, flexible compression ratio, simple arithmetic computation and full utilization of input sparsity. We propose PermDNN architecture, a multi-processing element (PE) fully-connected (FC) layer-targeted computing engine. The entire architecture is highly scalable and flexible, and hence it can support the needs of different applications with different model configurations. We implement a 32-PE design using CMOS 28nm technology. Compared with EIE, PermDNN achieves 3.3x ~ 4.8x higher throughout, 5.9x ~ 8.5x better area efficiency and 2.8x ~ 4.0x better energy efficiency on different workloads. Compared with CirCNN, PermDNN achieves 11.51x higher throughput and 3.89x better energy efficiency.

Action prediction is an important item in the fields of pattem recognition and computer vision. Capturing evolution tendency cues is a key point to action prediction. Dense trajectory (DT) and dynamic image are both effective approaches to explore dynamic information in videos. DT is used to describe the features of action and has achieved state-of-the-art results on action recognition, but often fails to capture trends of action. Dynamic image is good at catching action evolution trends, but its representation ability is slightly weak. This paper aims to extract an accurate representation on action evolution trends from videos, which is combined those two methods talked above. In addition, we build a classifier based on category dependency to select information to improve the accuracy of action prediction. Experimental results on public datasets demonstrate validity of the proposed algorithm.

Magnetic resonance imaging (MRI) can aid in assessing post-ablation scar formation. Automatic segmentation of left atrium (LA) offers great benefits for an accurate statistical assessment of LA region. However, how to robustly segment LA is still remaining as a challenging task for its high anatomical variability. In this paper, a robust segmentation method that exploits semantic information from different parts is proposed. The semantic correlation is exploited by the K Nearest Neighbor (KNN) search from corpus images with Convolutional Neural Network (CNN) features, which can be regarded as our main contribution. We propose a graph model to fuse semantic cues and eliminate accidental factors. Meanwhile, to optimize segmentation results, a super pixel voting method is also proposed. Experiments on public datasets of MRI image demonstrate the validity and accuracy of our semantic segmentation.

Object detection is a key issue in computer vision, and technologies based local descriptor become more and more mature, especially in pedestrian detection. In this paper, we present a novel algorithm to detect targets from an image. Local descriptor has been used in object detection for quite some time and proven to be a valuable tool. However, Local descriptors are usually accompanied by boundary effect and poor continuity. Our algorithm addresses these problems via utilizing the global descriptor, called Multi-viewpoint histogram (MVH), which is more likely to rotate and zoom. The challenge of using just the global descriptor is what can not provide enough global information and local information. Different from the previous researches, this study integrates sufficient global information and local information of image by multi-viewpoints and probability density function (PDF). The experimental results demonstrate that our algorithm has fared well in some publically available database, moreover, outperforms current state-of-the-art methods in some respects, such as image matching between different spectra images and in the case of the small targets.